void clk_init(void) { uint32_t cksel; /* in case of soft resets, disable watchdog */ sm_writel(WDT_CTRL, SM_BF(KEY, 0x55)); sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa)); #ifdef CONFIG_PLL /* Initialize the PLL */ sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES) | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1) | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1) | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT) | SM_BF(PLLOSC, 0) | SM_BIT(PLLEN))); /* Wait for lock */ while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; #endif /* Set up clocks for the CPU and all peripheral buses */ cksel = 0; if (CONFIG_SYS_CLKDIV_CPU) cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1); if (CONFIG_SYS_CLKDIV_HSB) cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1); if (CONFIG_SYS_CLKDIV_PBA) cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1); if (CONFIG_SYS_CLKDIV_PBB) cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1); sm_writel(PM_CKSEL, cksel); #ifdef CONFIG_PLL /* Use PLL0 as main clock */ sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); #endif }
unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, unsigned long rate, unsigned long parent_rate) { unsigned long divider; if (rate == 0 || parent_rate == 0) { sm_writel(PM_GCCTRL(id), 0); return 0; } divider = (parent_rate + rate / 2) / rate; if (divider <= 1) { sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN)); rate = parent_rate; } else { divider = min(255, divider / 2 - 1); sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN) | SM_BF(DIV, divider)); rate = parent_rate / (2 * (divider + 1)); } return rate; }
void pm_init(void) { uint32_t cksel = 0; unsigned long main_clock; /* Make sure we don't disable any device we're already using */ get_device(DEVICE_HRAMC); get_device(DEVICE_HEBI); /* Enable the PICO as well */ ckd_state[CLOCK_CPU].mask |= 1; gd->sm = get_device(DEVICE_SM); if (!gd->sm) panic("Unable to claim system manager device!\n"); /* Disable any devices that haven't been explicitly claimed */ sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask); sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask); sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask); sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask); #ifdef CONFIG_PLL /* Initialize the PLL */ main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL; sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) | SM_BF(PLLOPT, CFG_PLL0_OPT) | SM_BF(PLLOSC, 0) | SM_BIT(PLLEN))); /* Wait for lock */ while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ; #else main_clock = CFG_OSC0_HZ; #endif /* Set up clocks for the CPU and all peripheral buses */ if (CFG_CLKDIV_CPU) { cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU); } else { ckd_state[CLOCK_CPU].freq = main_clock; } if (CFG_CLKDIV_HSB) { cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB); } else { ckd_state[CLOCK_HSB].freq = main_clock; } if (CFG_CLKDIV_PBA) { cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA); } else { ckd_state[CLOCK_PBA].freq = main_clock; } if (CFG_CLKDIV_PBB) { cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB); } else { ckd_state[CLOCK_PBB].freq = main_clock; } sm_writel(gd->sm, PM_CKSEL, cksel); /* CFG_HZ currently depends on cpu_hz */ gd->cpu_hz = ckd_state[CLOCK_CPU].freq; #ifdef CONFIG_PLL /* Use PLL0 as main clock */ sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL)); #endif }