static void spi_write(ice1712_t *ice, unsigned int dev, unsigned int reg, unsigned int data)
{
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
spi_send_byte(ice, data); /* DATA */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
}
static void ak4396_write(struct snd_ice1712 *ice, unsigned int reg,
unsigned int data)
{
unsigned int block;
snd_ice1712_gpio_set_dir(ice, AK4396_CSN|AK4396_CCLK|AK4396_CDTI);
snd_ice1712_gpio_set_mask(ice, ~(AK4396_CSN|AK4396_CCLK|AK4396_CDTI));
set_gpio_bit(ice, AK4396_CSN, 0);
block = ((AK4396_ADDR & 0x03) << 14) | (1 << 13) |
((reg & 0x1f) << 8) | (data & 0xff);
ak4396_send_word(ice, block);
set_gpio_bit(ice, AK4396_CSN, 1);
udelay(1);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
}
static int pontis_gpio_data_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
down(&ice->gpio_mutex);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
up(&ice->gpio_mutex);
return 0;
}
static int pontis_gpio_data_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
mutex_lock(&ice->gpio_mutex);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
mutex_unlock(&ice->gpio_mutex);
return 0;
}
static void wm8766_spi_write(struct snd_ice1712 *ice, unsigned int reg,
unsigned int data)
{
unsigned int block;
snd_ice1712_gpio_set_dir(ice, WM8766_SPI_MD|
WM8766_SPI_CLK|WM8766_SPI_ML);
snd_ice1712_gpio_set_mask(ice, ~(WM8766_SPI_MD|
WM8766_SPI_CLK|WM8766_SPI_ML));
set_gpio_bit(ice, WM8766_SPI_ML, 0);
block = (reg << 9) | (data & 0x1ff);
wm8766_spi_send_word(ice, block);
set_gpio_bit(ice, WM8766_SPI_ML, 1);
udelay(1);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
}
static unsigned int spi_read(ice1712_t *ice, unsigned int dev, unsigned int reg)
{
unsigned int val;
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev | 1); /* READ */
val = spi_read_byte(ice);
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
return val;
}
static int pontis_gpio_data_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned int val, nval;
int changed = 0;
down(&ice->gpio_mutex);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
val = snd_ice1712_gpio_read(ice) & 0xffff;
nval = ucontrol->value.integer.value[0] & 0xffff;
if (val != nval) {
snd_ice1712_gpio_write(ice, nval);
changed = 1;
}
up(&ice->gpio_mutex);
return changed;
}
static void se200pci_WM8766_write(struct snd_ice1712 *ice,
unsigned int addr, unsigned int data)
{
unsigned int st;
unsigned int bits;
int i;
const unsigned int DATA = 0x010000;
const unsigned int CLOCK = 0x020000;
const unsigned int LOAD = 0x040000;
const unsigned int ALL_MASK = (DATA | CLOCK | LOAD);
snd_ice1712_save_gpio_status(ice);
st = ((addr & 0x7f) << 9) | (data & 0x1ff);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction | ALL_MASK);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask & ~ALL_MASK);
bits = snd_ice1712_gpio_read(ice) & ~ALL_MASK;
snd_ice1712_gpio_write(ice, bits);
for (i = 0; i < 16; i++) {
udelay(1);
bits &= ~CLOCK;
st = (st << 1);
if (st & 0x10000)
bits |= DATA;
else
bits &= ~DATA;
snd_ice1712_gpio_write(ice, bits);
udelay(1);
bits |= CLOCK;
snd_ice1712_gpio_write(ice, bits);
}
udelay(1);
bits |= LOAD;
snd_ice1712_gpio_write(ice, bits);
udelay(1);
bits |= (DATA | CLOCK);
snd_ice1712_gpio_write(ice, bits);
snd_ice1712_restore_gpio_status(ice);
}
static int __devinit phase28_init(struct snd_ice1712 *ice)
{
static const unsigned short wm_inits_phase28[] = {
/* These come first to reduce init pop noise */
0x1b, 0x044, /* ADC Mux (AC'97 source) */
0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
0x18, 0x000, /* All power-up */
0x16, 0x122, /* I2S, normal polarity, 24bit */
0x17, 0x022, /* 256fs, slave mode */
0x00, 0, /* DAC1 analog mute */
0x01, 0, /* DAC2 analog mute */
0x02, 0, /* DAC3 analog mute */
0x03, 0, /* DAC4 analog mute */
0x04, 0, /* DAC5 analog mute */
0x05, 0, /* DAC6 analog mute */
0x06, 0, /* DAC7 analog mute */
0x07, 0, /* DAC8 analog mute */
0x08, 0x100, /* master analog mute */
0x09, 0xff, /* DAC1 digital full */
0x0a, 0xff, /* DAC2 digital full */
0x0b, 0xff, /* DAC3 digital full */
0x0c, 0xff, /* DAC4 digital full */
0x0d, 0xff, /* DAC5 digital full */
0x0e, 0xff, /* DAC6 digital full */
0x0f, 0xff, /* DAC7 digital full */
0x10, 0xff, /* DAC8 digital full */
0x11, 0x1ff, /* master digital full */
0x12, 0x000, /* phase normal */
0x13, 0x090, /* unmute DAC L/R */
0x14, 0x000, /* all unmute */
0x15, 0x000, /* no deemphasis, no ZFLG */
0x19, 0x000, /* -12dB ADC/L */
0x1a, 0x000, /* -12dB ADC/R */
(unsigned short)-1
};
unsigned int tmp;
struct snd_akm4xxx *ak;
const unsigned short *p;
int i;
ice->num_total_dacs = 8;
ice->num_total_adcs = 2;
// Initialize analog chips
ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
if (!ak)
return -ENOMEM;
ice->akm_codecs = 1;
snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for the time being */
/* reset the wm codec as the SPI mode */
snd_ice1712_save_gpio_status(ice);
snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|PHASE28_HP_SEL));
tmp = snd_ice1712_gpio_read(ice);
tmp &= ~PHASE28_WM_RESET;
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
tmp |= PHASE28_WM_CS;
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
tmp |= PHASE28_WM_RESET;
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
p = wm_inits_phase28;
for (; *p != (unsigned short)-1; p += 2)
wm_put(ice, p[0], p[1]);
snd_ice1712_restore_gpio_status(ice);
ice->spec.phase28.master[0] = WM_VOL_MUTE;
ice->spec.phase28.master[1] = WM_VOL_MUTE;
for (i = 0; i < ice->num_total_dacs; i++) {
ice->spec.phase28.vol[i] = WM_VOL_MUTE;
wm_set_vol(ice, i, ice->spec.phase28.vol[i], ice->spec.phase28.master[i % 2]);
}
return 0;
}
