void soc_dma_reset(struct soc_dma_s *soc) { struct dma_s *s = (struct dma_s *) soc; s->soc.drqbmp = 0; s->ch_enable_mask = 0; s->enabled_count = 0; soc_dma_ch_freq_update(s); }
void soc_dma_reset(struct soc_dma_s *soc) { struct dma_s *s = (struct dma_s *) soc; memset(s->soc.drqst, 0, sizeof(s->soc.drqst)); s->ch_enable_mask = 0; s->enabled_count = 0; soc_dma_ch_freq_update(s); }
void soc_dma_set_request(struct soc_dma_ch_s *ch, int level) { struct dma_s *dma = (struct dma_s *) ch->dma; dma->enabled_count += level - ch->enable; if (level) dma->ch_enable_mask |= 1 << ch->num; else dma->ch_enable_mask &= ~(1 << ch->num); if (level != ch->enable) { soc_dma_ch_freq_update(dma); ch->enable = level; if (!ch->enable) qemu_del_timer(ch->timer); else if (!ch->running) soc_dma_ch_run(ch); else soc_dma_ch_schedule(ch, 1); } }