void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
	unsigned int count = entry_cnt;
	unsigned int tmp;

	for (; count > 0; count--){
		if(S5P_XUSBXTI_SYS != exynos4_pmu_config[count - 1].reg){
			__raw_writel(exynos4_pmu_config[count - 1].val[mode],
					exynos4_pmu_config[count - 1].reg);
		}
		else if(S5P_XUSBXTI_SYS == exynos4_pmu_config[count - 1].reg){
			//printk("++++++++++++Terry++++++++++call_flag=%d , mode=%d \n", tc4_get_call_flg(),mode);
			if((tc4_get_call_flg() != 1)||(mode != SYS_SLEEP)){
				//printk("%s ------Terry1--------close xclk------tc4_get_call_flg=%d---\n",__func__,tc4_get_call_flg());
				__raw_writel(exynos4_pmu_config[count - 1].val[mode],
						exynos4_pmu_config[count - 1].reg);
			}
			else
			{
				//printk("%s ------Terry2--------close xclk------tc4_get_call_flg=%d---\n",__func__,tc4_get_call_flg());
				__raw_writel(0x1, exynos4_pmu_config[count - 1].reg);
			}
		} 
	}

	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
		for (count = 0 ; count < ARRAY_SIZE(exynos4x12_c2c_pmu_conf) ; count++)
			__raw_writel(exynos4x12_c2c_pmu_conf[count].val[mode],
					exynos4x12_c2c_pmu_conf[count].reg);

		if (soc_is_exynos4212())
			__raw_writel(exynos4212_c2c_pmu_conf[0].val[mode],
					exynos4212_c2c_pmu_conf[0].reg);

		for (count = 0 ; count < ARRAY_SIZE(exynos4_config_for_c2c) ; count++) {
			printk("exynos4_config_for_c2c \n");

			tmp = __raw_readl(exynos4_config_for_c2c[count].reg);
			tmp |= exynos4_config_for_c2c[count].val;
			__raw_writel(tmp, exynos4_config_for_c2c[count].reg);
		}
	}
}
static int exynos_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
{
	struct dw_mci *host = (struct dw_mci *)data;

	/* Set Phase Shift Register */
	if (soc_is_exynos4210()) {
		host->pdata->sdr_timing = 0x00010001;
		host->pdata->ddr_timing = 0x00020002;
	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
		host->pdata->sdr_timing = 0x00010001;
		host->pdata->ddr_timing = 0x00010002;
	}
#ifdef CONFIG_SLP
	host->pdata->sdr_timing = 0x00020001;
	host->pdata->ddr_timing = 0x00020002;
#endif

	return 0;
}
Esempio n. 3
0
static int exynos_cpufreq_probe(struct platform_device *pdev)
{
	int ret = -EINVAL;

	exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL);
	if (!exynos_info)
		return -ENOMEM;

	if (soc_is_exynos4210())
		ret = exynos4210_cpufreq_init(exynos_info);
	else if (soc_is_exynos4212() || soc_is_exynos4412())
		ret = exynos4x12_cpufreq_init(exynos_info);
	else if (soc_is_exynos5250())
		ret = exynos5250_cpufreq_init(exynos_info);
	else
		return 0;

	if (ret)
		goto err_vdd_arm;

	if (exynos_info->set_freq == NULL) {
		pr_err("%s: No set_freq function (ERR)\n", __func__);
		goto err_vdd_arm;
	}

	arm_regulator = regulator_get(NULL, "vdd_arm");
	if (IS_ERR(arm_regulator)) {
		pr_err("%s: failed to get resource vdd_arm\n", __func__);
		goto err_vdd_arm;
	}

	/* Done here as we want to capture boot frequency */
	locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000;

	if (!cpufreq_register_driver(&exynos_driver))
		return 0;

	pr_err("%s: failed to register cpufreq driver\n", __func__);
	regulator_put(arm_regulator);
err_vdd_arm:
	kfree(exynos_info);
	return -EINVAL;
}
Esempio n. 4
0
void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
				struct i2c_board_info *mhl_info, int mhl_bus)
{
	struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;

	if (soc_is_exynos4210())
		pd->hdmiphy_bus = 8;
	else if (soc_is_s5pv210())
		pd->hdmiphy_bus = 3;
	else
		pd->hdmiphy_bus = 0;

	pd->hdmiphy_info = hdmiphy_info;
	pd->mhl_info = mhl_info;
	pd->mhl_bus = mhl_bus;

	s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
				&s5p_device_hdmi);
}
Esempio n. 5
0
void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
{
	struct s3c2410_platform_i2c *npd;

	if (!pd) {
		pd = &default_i2c_data;

		if (soc_is_exynos4210() ||
		    soc_is_exynos4212() || soc_is_exynos4412())
			pd->bus_num = 8;
		else if (soc_is_s5pv210())
			pd->bus_num = 3;
		else
			pd->bus_num = 0;
	}

	npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
			       &s5p_device_i2c_hdmiphy);
}
Esempio n. 6
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int __init exynos4_init(void)
{
    unsigned int value;
    unsigned int tmp;
    unsigned int i;

    printk(KERN_INFO "EXYNOS4: Initializing architecture\n");

    /* set idle function */
    pm_idle = exynos4_idle;

    /*
     * on exynos4x12, CMU reset system power register should to be set 0x0
     */
    if (!soc_is_exynos4210()) {
        for (i = 0; i < ARRAY_SIZE(exynos4_pmu_init_zero); i++)
            __raw_writel(0x0, exynos4_pmu_init_zero[i]);
    }

    /* set sw_reset function */
    s5p_reset_hook = exynos4_sw_reset;

    /* Disable auto wakeup from power off mode */
    for (i = 0; i < num_possible_cpus(); i++) {
        tmp = __raw_readl(S5P_ARM_CORE_OPTION(i));
        tmp &= ~S5P_CORE_OPTION_DIS;
        __raw_writel(tmp, S5P_ARM_CORE_OPTION(i));
    }

    if (soc_is_exynos4212() || soc_is_exynos4412()) {
        value = __raw_readl(S5P_AUTOMATIC_WDT_RESET_DISABLE);
        value &= ~S5P_SYS_WDTRESET;
        __raw_writel(value, S5P_AUTOMATIC_WDT_RESET_DISABLE);
        value = __raw_readl(S5P_MASK_WDT_RESET_REQUEST);
        value &= ~S5P_SYS_WDTRESET;
        //__raw_writel(value, S5P_MASK_WDT_RESET_REQUEST);
        //Temperory ignore ISP reset, for ISP test. Jiangshanbin120405
        __raw_writel((value | (1<< 26)), S5P_MASK_WDT_RESET_REQUEST);

    }

    return sysdev_register(&exynos4_sysdev);
}
static int tmu_initialize(struct platform_device *pdev)
{
	struct tmu_info *info = platform_get_drvdata(pdev);
	unsigned int en;
	int ret;

	en = (__raw_readl(info->tmu_base + TMU_STATUS) & 0x1);

	if (!en) {
		dev_err(&pdev->dev, "failed to start tmu drvier\n");
		return -ENOENT;
	}

	if (soc_is_exynos4210())
		ret = exynos4210_tmu_init(info);
	else
		ret = exynos_tmu_init(info);

	return ret;
}
static int exynos_usb_phy_clock_enable(struct platform_device *pdev)
{
	int err;

	if (!phy_clk) {
		if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
			phy_clk = clk_get(&pdev->dev, "usbotg");
		else
			phy_clk = clk_get(&pdev->dev, "usbhost");

		if (IS_ERR(phy_clk)) {
			dev_err(&pdev->dev, "Failed to get phy clock\n");
			return PTR_ERR(phy_clk);
		}
	}

	err = clk_enable(phy_clk);

	return err;
}
static int exynos4_usb_phy1_suspend(struct platform_device *pdev)
{
	u32 phypwr;

	/* set to suspend HSIC 0 and 1 and standard of PHY1 */
	phypwr = readl(EXYNOS4_PHYPWR);
	if (soc_is_exynos4210()) {
		phypwr |= (PHY1_STD_FORCE_SUSPEND
			| EXYNOS4210_HSIC0_FORCE_SUSPEND
			| EXYNOS4210_HSIC1_FORCE_SUSPEND);
	} else {
		phypwr = readl(EXYNOS4_PHYPWR);
		phypwr |= (PHY1_STD_FORCE_SUSPEND
			| EXYNOS4212_HSIC0_FORCE_SUSPEND
			| EXYNOS4212_HSIC1_FORCE_SUSPEND);
	}
	writel(phypwr, EXYNOS4_PHYPWR);

	return 0;
}
Esempio n. 10
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static int tmu_initialize(struct platform_device *pdev)
{
	struct s5p_tmu_info *info = platform_get_drvdata(pdev);
	unsigned int tmp;
	unsigned ret;

	/* check if sensing is idle */
	tmp = (__raw_readl(info->tmu_base + EXYNOS4_TMU_STATUS) & 0x1);
	if (!tmp) {
		pr_err("failed to start tmu driver\n");
		return -ENOENT;
	}

	if (soc_is_exynos4210())
		ret = exynos4210_tmu_init(info);
	else
		ret = exynos4x12_tmu_init(info);

	return ret;
}
Esempio n. 11
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void __init s5p_fimg2d_set_platdata(struct fimg2d_platdata *pd)
{
	struct fimg2d_platdata *npd;

	if (soc_is_exynos4210()) {
		s5p_fimg2d_resource[0].start = S5P_PA_FIMG2D_3X;
		s5p_fimg2d_resource[0].end = S5P_PA_FIMG2D_3X + SZ_4K - 1;
	}

	if (!pd)
		pd = &default_fimg2d_data;

	if (samsung_rev() == EXYNOS4412_REV_2_0)
		pd->clkrate = 221 * MHZ;	/* 220 Mhz */

	npd = kmemdup(pd, sizeof(*pd), GFP_KERNEL);
	if (!npd)
		printk(KERN_ERR "no memory for fimg2d platform data\n");
	else
		s5p_device_fimg2d.dev.platform_data = npd;
}
Esempio n. 12
0
static int __init exynos4_l2x0_cache_init(void)
{
	/* TAG, Data Latency Control: 2cycle */
	__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);

	if (soc_is_exynos4210())
		__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
	else if (soc_is_exynos4212() || soc_is_exynos4412())
		__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);

	/* L2X0 Prefetch Control */
	__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);

	/* L2X0 Power Control */
	__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
		     S5P_VA_L2CC + L2X0_POWER_CTRL);

	l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);

	return 0;
}
static void exynos4_cpu_prepare(void)
{
	if (exynos4_sleep_gpio_table_set)
		exynos4_sleep_gpio_table_set();

	/* Set value of power down register for sleep mode */

	exynos4_sys_powerdown_conf(SYS_SLEEP);
	__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);

	/* ensure at least INFORM0 has the resume address */

	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);

	/* Before enter central sequence mode, clock src register have to set */

	s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));

	if (soc_is_exynos4210())
		s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
}
Esempio n. 14
0
void s3c_fimc0_cfg_gpio(struct platform_device *pdev)
{
#if defined(CONFIG_MACH_SMDK4212) || defined(CONFIG_MACH_SMDK4210)
	if (soc_is_exynos4210()) {
		/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ0(0), 8, S3C_GPIO_SFN(2));
		/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ1(0), 5, S3C_GPIO_SFN(2));
		/* CAM B port(b0011) : DATA[0-7] */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE1(0), 8, S3C_GPIO_SFN(3));
		/* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLKOUT */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE0(0), 5, S3C_GPIO_SFN(3));
	} else {
		/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ0(0), 8, S3C_GPIO_SFN(2));
		/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ1(0), 5, S3C_GPIO_SFN(2));
		/* CAM B port(b0011) : PCLK, DATA[0-6] */
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM0(0), 8, S3C_GPIO_SFN(3));
		/* CAM B port(b0011) : FIELD, DATA[7]*/
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM1(0), 2, S3C_GPIO_SFN(3));
		/* CAM B port(b0011) : VSYNC, HREF, CLKOUT*/
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM2(0), 3, S3C_GPIO_SFN(3));
	}
	/* note : driver strength to max is unnecessary */
#elif defined(CONFIG_MACH_PX)
	/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
	s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ0(0), 8, S3C_GPIO_SFN(2));
	/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
	s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ1(0), 5, S3C_GPIO_SFN(2));
	/* Disable Mclk */
	s3c_gpio_cfgpin(EXYNOS4210_GPJ1(3), S3C_GPIO_INPUT);
	s3c_gpio_setpull(EXYNOS4210_GPJ1(3), S3C_GPIO_PULL_DOWN);

	/* CAM B port(b0011) : DATA[0-7] */
	s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE1(0), 8, S3C_GPIO_SFN(3));
	/* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLKOUT */
	s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE0(0), 5, S3C_GPIO_SFN(3));
#endif
}
static void pm_tmu_restore(struct tmu_info *info)
{
	if (soc_is_exynos4210()) {
		__raw_writel(info->reg_save[9], info->tmu_base + TRIG_LEV3);
		__raw_writel(info->reg_save[8], info->tmu_base + TRIG_LEV2);
		__raw_writel(info->reg_save[7], info->tmu_base + TRIG_LEV1);
		__raw_writel(info->reg_save[6], info->tmu_base + TRIG_LEV0);
		__raw_writel(info->reg_save[5], info->tmu_base	\
						+ THRESHOLD_TEMP);
	} else {
#if defined(CONFIG_TC_VOLTAGE)
		 __raw_writel(info->reg_save[6], info->tmu_base \
						+ THD_TEMP_FALL);
#endif
		__raw_writel(info->reg_save[5], info->tmu_base + THD_TEMP_RISE);
	}
	__raw_writel(info->reg_save[4], info->tmu_base + INTEN);
	__raw_writel(info->reg_save[3], info->tmu_base + CNT_VALUE1);
	__raw_writel(info->reg_save[2], info->tmu_base + CNT_VALUE0);
	__raw_writel(info->reg_save[0], info->tmu_base + TMU_CON);
	__raw_writel(info->reg_save[1], info->tmu_base + SAMPLING_INTERNAL);
}
Esempio n. 16
0
void s3c_fimc0_cfg_gpio(struct platform_device *pdev)
{
	if (soc_is_exynos4210()) {
#if defined (CONFIG_MX_SERIAL_TYPE)
		/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ0(0), 8, S3C_GPIO_SFN(2));
		/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ1(0), 4, S3C_GPIO_SFN(2));
#else
		/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ0(0), 8, S3C_GPIO_SFN(2));
		/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ1(0), 5, S3C_GPIO_SFN(2));
		/* CAM B port(b0011) : DATA[0-7] */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE1(0), 8, S3C_GPIO_SFN(3));
		/* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLKOUT */
		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE0(0), 5, S3C_GPIO_SFN(3));
#endif
	} else {
#if defined(CONFIG_MX_SERIAL_TYPE)
		/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ0(0), 8, S3C_GPIO_SFN(2));		
		/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ1(0), 4, S3C_GPIO_SFN(2));

		/* CAM B port(b0011) : PCLK, DATA[0-6] */
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM0(0), 8, S3C_GPIO_SFN(3));
		/* CAM B port(b0011) : FIELD, DATA[7]*/
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM1(0), 2, S3C_GPIO_SFN(3));
		/* CAM B port(b0011) : VSYNC, HREF, CLKOUT*/
		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM2(0), 3, S3C_GPIO_SFN(3));
#endif

#if defined(CONFIG_MX2_SERIAL_TYPE)
		s3c_gpio_cfgpin(EXYNOS4212_GPJ1(3), S3C_GPIO_SFN(2));
#endif
	}
	/* note : driver strength to max is unnecessary */
}
int s5p_usb_phy_resume(struct platform_device *pdev, int type)
{
    int ret = 0;
#ifdef CONFIG_USB_OHCI_S5P
    u32 phyclk;
#endif
    if (exynos_usb_phy_clock_enable(pdev))
        return 0;

    mutex_lock(&phy_lock);

    if (usb_phy_control.flags)
        goto done;

    if (type == S5P_USB_PHY_HOST) {
        if (soc_is_exynos4210() ||
                soc_is_exynos4212() ||
                soc_is_exynos4412()) {
#ifdef CONFIG_USB_OHCI_S5P
            phyclk = readl(EXYNOS4_PHYCLK);
            phyclk |= PHY1_COMMON_ON_N;
            writel(phyclk, EXYNOS4_PHYCLK);
#endif
            ret = exynos4_usb_phy1_resume(pdev);
        } else
            ret = exynos5_usb_phy_host_resume(pdev);
    }
done:
    if (!strcmp(pdev->name, "s5p-ehci"))
        set_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
    else if (!strcmp(pdev->name, "s5p-ohci"))
        set_bit(HOST_PHY_OHCI, &usb_phy_control.flags);

    mutex_unlock(&phy_lock);
    exynos_usb_phy_clock_disable(pdev);

    return ret;
}
static void pm_tmu_save(struct tmu_info *info)
{
	info->reg_save[0] = __raw_readl(info->tmu_base + TMU_CON);
	info->reg_save[1] = __raw_readl(info->tmu_base + SAMPLING_INTERNAL);
	info->reg_save[2] = __raw_readl(info->tmu_base + CNT_VALUE0);
	info->reg_save[3] = __raw_readl(info->tmu_base + CNT_VALUE1);
	info->reg_save[4] = __raw_readl(info->tmu_base + INTEN);

	if (soc_is_exynos4210()) {
		info->reg_save[5] = __raw_readl(info->tmu_base	\
						+ THRESHOLD_TEMP);
		info->reg_save[6] = __raw_readl(info->tmu_base + TRIG_LEV0);
		info->reg_save[7] = __raw_readl(info->tmu_base + TRIG_LEV1);
		info->reg_save[8] = __raw_readl(info->tmu_base + TRIG_LEV2);
		info->reg_save[9] = __raw_readl(info->tmu_base + TRIG_LEV3);
	} else {
		info->reg_save[5] = __raw_readl(info->tmu_base + THD_TEMP_RISE);
#if defined(CONFIG_TC_VOLTAGE)
		info->reg_save[6] = __raw_readl(info->tmu_base
					+ THD_TEMP_FALL);
#endif
	}
}
Esempio n. 19
0
static void exynos4_pm_prepare(void)
{
	/* Set value of power down register for sleep mode */

	exynos4_sys_powerdown_conf(SYS_SLEEP);
	__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);

	/* ensure at least INFORM0 has the resume address */

	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);

	/* Before enter central sequence mode, clock src register have to set */

#ifdef CONFIG_CACHE_L2X0
	/* Disable the full line of zero */
	disable_cache_foz();
#endif

	s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));

	if (soc_is_exynos4210())
		s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
}
Esempio n. 20
0
static void __init exynos4_map_io(void)
{
    iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));

    if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
        iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
    else
        iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));

    /* initialize device information early */
    exynos4_default_sdhci0();
    exynos4_default_sdhci1();
    exynos4_default_sdhci2();
    exynos4_default_sdhci3();

    s3c_adc_setname("samsung-adc-v3");

    s3c_fimc_setname(0, "exynos4-fimc");
    s3c_fimc_setname(1, "exynos4-fimc");
    s3c_fimc_setname(2, "exynos4-fimc");
    s3c_fimc_setname(3, "exynos4-fimc");

    s3c_sdhci_setname(0, "exynos4-sdhci");
    s3c_sdhci_setname(1, "exynos4-sdhci");
    s3c_sdhci_setname(2, "exynos4-sdhci");
    s3c_sdhci_setname(3, "exynos4-sdhci");

    /* The I2C bus controllers are directly compatible with s3c2440 */
    s3c_i2c0_setname("s3c2440-i2c");
    s3c_i2c1_setname("s3c2440-i2c");
    s3c_i2c2_setname("s3c2440-i2c");

    s5p_fb_setname(0, "exynos4-fb");
    s5p_hdmi_setname("exynos4-hdmi");

    s3c64xx_spi_setname("exynos4210-spi");
}
Esempio n. 21
0
static int exynos4_usb_phy1_suspend(struct platform_device *pdev)
{
	struct clk *otg_clk;
	u32 phypwr;
	int err;

	otg_clk = clk_get(&pdev->dev, "usbotg");
	if (IS_ERR(otg_clk)) {
		dev_err(&pdev->dev, "Failed to get otg clock\n");
		return PTR_ERR(otg_clk);
	}

	err = clk_enable(otg_clk);
	if (err) {
		clk_put(otg_clk);
		return err;
	}

	/* set to suspend HSIC 0 and 1 and standard of PHY1 */
	phypwr = readl(EXYNOS4_PHYPWR);
	if (soc_is_exynos4210()) {
		phypwr |= (PHY1_STD_FORCE_SUSPEND
			| EXYNOS4210_HSIC0_FORCE_SUSPEND
			| EXYNOS4210_HSIC1_FORCE_SUSPEND);
	} else {
		phypwr = readl(EXYNOS4_PHYPWR);
		phypwr |= (PHY1_STD_FORCE_SUSPEND
			| EXYNOS4212_HSIC0_FORCE_SUSPEND
			| EXYNOS4212_HSIC1_FORCE_SUSPEND);
	}
	writel(phypwr, EXYNOS4_PHYPWR);

	clk_disable(otg_clk);
	clk_put(otg_clk);

	return 0;
}
Esempio n. 22
0
void __init exynos_dwmci_set_platdata(struct dw_mci_board *pd)
{
	struct dw_mci_board *npd = NULL;

	if ((soc_is_exynos4210()) ||
		soc_is_exynos4212() || soc_is_exynos4412()) {
		npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board), &exynos_device_dwmci);
	} else {
		printk("dwmci platform data support only exynos4/5!\n");
#ifdef CONFIG_SLP
	npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
			&exynos_device_dwmci);
#endif
	}

	if (npd) {
	if (!npd->init)
		npd->init = exynos_dwmci_init;
	if (!npd->get_bus_wd)
		npd->get_bus_wd = exynos_dwmci_get_bus_wd;
		if (!npd->set_io_timing)
			npd->set_io_timing = exynos_dwmci_set_io_timing;
	}
}
int s5p_usb_phy_suspend(struct platform_device *pdev, int type)
{
	int ret = 0;
#ifdef CONFIG_USB_OHCI_S5P
	struct s5p_ohci_hcd *s5p_ohci = platform_get_drvdata(&s5p_device_ohci);
	struct usb_hcd *ohci_hcd = s5p_ohci->hcd;
	u32 phyclk;
#endif

	if (exynos_usb_phy_clock_enable(pdev))
		return 0;

	mutex_lock(&phy_lock);

	if (!strcmp(pdev->name, "s5p-ehci"))
		clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
	else if (!strcmp(pdev->name, "s5p-ohci"))
		clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);

	if (usb_phy_control.flags)
		goto done;

	if (type == S5P_USB_PHY_HOST) {
		if (soc_is_exynos4210() ||
			soc_is_exynos4212() ||
			soc_is_exynos4412())
			ret = exynos4_usb_phy1_suspend(pdev);
		else
			ret = exynos5_usb_phy_host_suspend(pdev);
	}
done:
	mutex_unlock(&phy_lock);
	exynos_usb_phy_clock_disable(pdev);

	return ret;
}
Esempio n. 24
0
static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
{
	/* configure GPIO for i2s port */
	struct exynos_gpio_cfg exynos4_cfg[3] = {
				{ EXYNOS4_GPZ(0),  7, S3C_GPIO_SFN(2) },
				{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2) },
				{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(2) }
	};
	struct exynos_gpio_cfg exynos5_cfg[3] = {
				{ EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
				{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
				{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
	};
	struct exynos_gpio_cfg exynos5410_cfg[3] = {
				{ EXYNOS5410_GPZ(0),  7, S3C_GPIO_SFN(2) },
				{ EXYNOS5410_GPB0(0), 5, S3C_GPIO_SFN(2) },
				{ EXYNOS5410_GPB1(0), 5, S3C_GPIO_SFN(2) }
	};

	if (pdev->id < 0 || pdev->id > 2) {
		printk(KERN_ERR "Invalid Device %d\n", pdev->id);
		return -EINVAL;
	}

	if (soc_is_exynos5250())
		s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,
			exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);
	else if (soc_is_exynos5410())
		s3c_gpio_cfgpin_range(exynos5410_cfg[pdev->id].addr,
			exynos5410_cfg[pdev->id].num, exynos5410_cfg[pdev->id].bit);
	else if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
		s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,
			exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);

	return 0;
}
Esempio n. 25
0
static int __init exynos4_l2x0_cache_init(void)
{
    u32 tag_latency = 0x110;
    u32 data_latency = soc_is_exynos4210() ? 0x110 : 0x120;
    u32 prefetch = (soc_is_exynos4412() &&
                    samsung_rev() >= EXYNOS4412_REV_1_0) ?
                   0x71000007 : 0x30000007;
    u32 aux_val = 0x7C470001;
    u32 aux_mask = 0xC200FFFF;

#ifdef CONFIG_ARM_TRUSTZONE
    exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch);
    exynos_smc(SMC_CMD_L2X0SETUP2,
               L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
               aux_val, aux_mask);
    exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
    exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
#else
    __raw_writel(tag_latency, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
    __raw_writel(data_latency, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
    __raw_writel(prefetch, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
    __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
                 S5P_VA_L2CC + L2X0_POWER_CTRL);
#endif

    l2x0_init(S5P_VA_L2CC, aux_val, aux_mask);

#ifdef CONFIG_ARM_TRUSTZONE
#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
    outer_cache.set_debug = exynos4_l2x0_set_debug;
#endif
#endif
    /* Enable the full line of zero */
    enable_cache_foz();
    return 0;
}
Esempio n. 26
0
static void exynos4_pm_resume(void)
{
	unsigned long tmp;
	void __iomem *inform1;

	/* If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
		/* No need to perform below restore code */
		pr_info("%s: early_wakeup\n", __func__);
		goto early_wakeup;
	}

	/* For release retention */

	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);

	s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save));
	if (soc_is_exynos4210())
		s3c_pm_do_restore(exynos4210_regs_save,
					ARRAY_SIZE(exynos4210_regs_save));
	else
		s3c_pm_do_restore(exynos4x12_regs_save,
					ARRAY_SIZE(exynos4x12_regs_save));

	if (!exynos4_is_c2c_use())
		s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
	else {
		if (!soc_is_exynos4210()) {
			/* Gating CLK_SSS */
			tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
			tmp &= ~(0x1 << 4);
			__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
		}
	}

	tmp = __raw_readl(S5P_WAKEUP_STAT);
	if (WARN_ON(!tmp) && soc_is_exynos4412()) {
		__raw_writel(__raw_readl(S5P_EINT_PEND(0)), S5P_EINT_PEND(0));
		__raw_writel(__raw_readl(S5P_EINT_PEND(1)), S5P_EINT_PEND(1));
		__raw_writel(__raw_readl(S5P_EINT_PEND(2)), S5P_EINT_PEND(2));
		__raw_writel(__raw_readl(S5P_EINT_PEND(3)), S5P_EINT_PEND(3));
		__raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0));
		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1));
		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2));
		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(3));
	}

#ifdef CONFIG_HAVE_ARM_SCU
	scu_enable(S5P_VA_SCU);
#endif

#ifdef CONFIG_CACHE_L2X0
	if (trustzone_on()) {
		/*
		 * Restore for Outer cache
		 */
		exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val,
					       exynos4_l2cc_save[1].val,
					       exynos4_l2cc_save[2].val);

		exynos_smc(SMC_CMD_L2X0SETUP2,
				L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
				0x7C470001, 0xC200FFFF);

		exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
		exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
	} else {
		s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
		outer_inv_all();
		/* enable L2X0*/
		writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
	}
#endif

early_wakeup:
	if (!soc_is_exynos4210())
		exynos4_reset_assert_ctrl(1);

#ifdef CONFIG_CACHE_L2X0
	/* Enable the full line of zero */
	enable_cache_foz();
#endif

	if (trustzone_on()) {
		inform1 = S5P_VA_SYSRAM_NS + 0xC;
	} else {
		inform1 = S5P_INFORM1;
	}

	/* Clear Check mode */
	__raw_writel(0x0, inform1);

	return;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
	u32 rstcon;
	u32 phypwr;
	int err;

#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
	/* HSIC LPA: reset-resume, let cp know pda active from LPA */
	/* slave wake at lpa wake ??? */
	/* 12.04.27 Move start of phy1_resume, If usb cable power on the
	 * host phy, EHCI resume miss the PDA_ACTVIE, then CP can't send Host
	 * wakeup Irq */
	if (!strcmp(pdev->name, "s5p-ehci"))
		set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif

	if (exynos4_usb_host_phy_is_on()) {
		/* set to resume HSIC 0 and 1 and standard of PHY1 */
		phypwr = readl(EXYNOS4_PHYPWR);
		if (soc_is_exynos4210()) {
			phypwr &= ~(PHY1_STD_FORCE_SUSPEND
				| EXYNOS4210_HSIC0_FORCE_SUSPEND
				| EXYNOS4210_HSIC1_FORCE_SUSPEND);
		} else {
			phypwr = readl(EXYNOS4_PHYPWR);
			phypwr &= ~(PHY1_STD_FORCE_SUSPEND
				| EXYNOS4212_HSIC0_FORCE_SUSPEND
				| EXYNOS4212_HSIC1_FORCE_SUSPEND);
		}
		writel(phypwr, EXYNOS4_PHYPWR);
		if (usb_phy_control.lpa_entered) {
			usb_phy_control.lpa_entered = 0;
			err = 1;
		} else
			err = 0;
	} else {
		phypwr = readl(EXYNOS4_PHYPWR);
		/* set to normal HSIC 0 and 1 of PHY1 */
		if (soc_is_exynos4210()) {
			writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);

			phypwr &= ~(PHY1_STD_NORMAL_MASK
				| EXYNOS4210_HSIC0_NORMAL_MASK
				| EXYNOS4210_HSIC1_NORMAL_MASK);
			writel(phypwr, EXYNOS4_PHYPWR);

			/* reset all ports of both PHY and Link */
			rstcon = readl(EXYNOS4_RSTCON)
				| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
				| EXYNOS4210_PHY1_SWRST_MASK;
			writel(rstcon, EXYNOS4_RSTCON);
			udelay(10);

			rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
				| EXYNOS4210_PHY1_SWRST_MASK);
			writel(rstcon, EXYNOS4_RSTCON);
		} else {
			exynos_usb_phy_control(USB_PHY
				| USB_PHY_HSIC0
				| USB_PHY_HSIC1,
				PHY_ENABLE);

			/* set to normal of Device */
			phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
			writel(phypwr, EXYNOS4_PHYPWR);

			/* reset both PHY and Link of Device */
			rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
			writel(rstcon, EXYNOS4_RSTCON);
			udelay(10);
			rstcon &= ~PHY0_SWRST_MASK;
			writel(rstcon, EXYNOS4_RSTCON);

			/* set to normal of Host */
			phypwr &= ~(PHY1_STD_NORMAL_MASK
				| EXYNOS4212_HSIC0_NORMAL_MASK
				| EXYNOS4212_HSIC1_NORMAL_MASK);
			writel(phypwr, EXYNOS4_PHYPWR);

			/* reset all ports of both PHY and Link */
			rstcon = readl(EXYNOS4_RSTCON)
				| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
				| EXYNOS4212_PHY1_SWRST_MASK;
			writel(rstcon, EXYNOS4_RSTCON);
			udelay(10);

			rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
				| EXYNOS4212_PHY1_SWRST_MASK);
			writel(rstcon, EXYNOS4_RSTCON);
		}
		usb_phy_control.lpa_entered = 0;
		err = 1;
	}
	udelay(80);

	return err;
}
static int __init exynos_dma_init(void)
{
	if (of_have_populated_dt())
		return 0;

	if (soc_is_exynos4210()) {
		exynos_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4210_pdma0_peri);
		exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
		exynos_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4210_pdma1_peri);
		exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
		exynos_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4212_pdma0_peri);
		exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
		exynos_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4212_pdma1_peri);
		exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
	} else if (soc_is_exynos4415()) {
		exynos_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4415_pdma0_peri);
		exynos_pdma0_pdata.peri_id = exynos4415_pdma0_peri;
		exynos_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4415_pdma1_peri);
		exynos_pdma1_pdata.peri_id = exynos4415_pdma1_peri;
	} else if (soc_is_exynos5250()) {
		exynos_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos5250_pdma0_peri);
		exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
		exynos_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos5250_pdma1_peri);
		exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
	} else if (soc_is_exynos5410()) {
		exynos_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos5410_pdma0_peri);
		exynos_pdma0_pdata.peri_id = exynos5410_pdma0_peri;
		exynos_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos5410_pdma1_peri);
		exynos_pdma1_pdata.peri_id = exynos5410_pdma1_peri;
	} else if (soc_is_exynos5420()) {
		exynos_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos5420_pdma0_peri);
		exynos_pdma0_pdata.peri_id = exynos5420_pdma0_peri;
		exynos_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos5420_pdma1_peri);
		exynos_pdma1_pdata.peri_id = exynos5420_pdma1_peri;
		exynos_adma0_pdata.nr_valid_peri =
			ARRAY_SIZE(adma0_peri);
		exynos_adma0_pdata.peri_id = adma0_peri;
	} else if (soc_is_exynos5260()) {
		exynos5260_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos5260_pdma0_peri);
		exynos5260_pdma0_pdata.peri_id = exynos5260_pdma0_peri;
	} else if (soc_is_exynos3470()) {
		exynos_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos3470_pdma0_peri);
		exynos_pdma0_pdata.peri_id = exynos3470_pdma0_peri;
		exynos_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos3470_pdma1_peri);
		exynos_pdma1_pdata.peri_id = exynos3470_pdma1_peri;
	} else if (soc_is_exynos3250()) {
		exynos_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos3250_pdma0_peri);
		exynos_pdma0_pdata.peri_id = exynos3250_pdma0_peri;
		exynos_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos3250_pdma1_peri);
		exynos_pdma1_pdata.peri_id = exynos3250_pdma1_peri;
	}

	if (soc_is_exynos4210() || soc_is_exynos4212() ||
		soc_is_exynos4412() || soc_is_exynos3470()) {
		exynos_pdma0_device.res.start = EXYNOS4_PA_PDMA0;
		exynos_pdma0_device.res.end = EXYNOS4_PA_PDMA0 + SZ_4K;
		exynos_pdma0_device.irq[0] = EXYNOS4_IRQ_PDMA0;
		exynos_pdma1_device.res.start = EXYNOS4_PA_PDMA1;
		exynos_pdma1_device.res.end = EXYNOS4_PA_PDMA1 + SZ_4K;
		exynos_pdma1_device.irq[0] = EXYNOS4_IRQ_PDMA1;
		exynos_mdma_device.res.start = EXYNOS4_PA_MDMA1;
		exynos_mdma_device.res.end = EXYNOS4_PA_MDMA1 + SZ_4K;
		exynos_mdma_device.irq[0] = EXYNOS4_IRQ_MDMA1;
	} else if (soc_is_exynos5410() || soc_is_exynos5420()) {
		exynos_mdma_device.res.start = EXYNOS5_PA_MDMA0;
		exynos_mdma_device.res.end = EXYNOS5_PA_MDMA0 + SZ_4K;
		exynos_mdma_device.irq[0] = EXYNOS5_IRQ_MDMA0;
	} else if (soc_is_exynos5260()) {
		exynos5260_pdma0_device.res.start = EXYNOS5260_PA_PDMA0;
		exynos5260_pdma0_device.res.end = EXYNOS5260_PA_PDMA0 + SZ_4K;
		exynos5260_pdma0_device.irq[0] = EXYNOS5260_IRQ_PDMA0;
		exynos5260_mdma_device.res.start = EXYNOS5260_PA_NS_MDMA0;
		exynos5260_mdma_device.res.end = EXYNOS5260_PA_NS_MDMA0 + SZ_4K;
		exynos5260_mdma_device.irq[0] = EXYNOS5260_IRQ_MDMA_1;
		exynos5260_adma_device.res.start = EXYNOS5260_PA_ADMA0;
		exynos5260_adma_device.res.end = EXYNOS5260_PA_ADMA0 + SZ_4K;
		exynos5260_adma_device.irq[0] = EXYNOS5260_IRQ_ADMA;
	} else if (soc_is_exynos4415()) {
		exynos_pdma0_device.res.start = EXYNOS4_PA_PDMA0;
		exynos_pdma0_device.res.end = EXYNOS4_PA_PDMA0 + SZ_4K;
		exynos_pdma0_device.irq[0] = EXYNOS4_IRQ_PDMA0;
		exynos_pdma1_device.res.start = EXYNOS4_PA_PDMA1;
		exynos_pdma1_device.res.end = EXYNOS4_PA_PDMA1 + SZ_4K;
		exynos_pdma1_device.irq[0] = EXYNOS4_IRQ_PDMA1;
		exynos_mdma_device.res.start = EXYNOS4_PA_MDMA1;
		exynos_mdma_device.res.end = EXYNOS4_PA_MDMA1 + SZ_4K;
		exynos_mdma_device.irq[0] = EXYNOS4_IRQ_MDMA1;
	} else if (soc_is_exynos3250()) {
		exynos_pdma0_device.res.start = EXYNOS3_PA_PDMA0;
		exynos_pdma0_device.res.end = EXYNOS3_PA_PDMA0 + SZ_4K;
		exynos_pdma0_device.irq[0] = EXYNOS3_IRQ_PDMA0;
		exynos_pdma1_device.res.start = EXYNOS3_PA_PDMA1;
		exynos_pdma1_device.res.end = EXYNOS3_PA_PDMA1 + SZ_4K;
		exynos_pdma1_device.irq[0] = EXYNOS3_IRQ_PDMA1;
	}

	if (soc_is_exynos5260()) {
		dma_cap_set(DMA_SLAVE, exynos5260_pdma0_pdata.cap_mask);
		dma_cap_set(DMA_CYCLIC, exynos5260_pdma0_pdata.cap_mask);
		amba_device_register(&exynos5260_pdma0_device, &iomem_resource);

		dma_cap_set(DMA_MEMCPY, exynos5260_mdma_pdata.cap_mask);
		amba_device_register(&exynos5260_mdma_device, &iomem_resource);

		dma_cap_set(DMA_SLAVE, exynos5260_adma_pdata.cap_mask);
		dma_cap_set(DMA_CYCLIC, exynos5260_adma_pdata.cap_mask);
		amba_device_register(&exynos5260_adma_device, &iomem_resource);
	} else if (soc_is_exynos3250()) {
		dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
		dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
		amba_device_register(&exynos_pdma0_device, &iomem_resource);

		dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
		dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
		amba_device_register(&exynos_pdma1_device, &iomem_resource);
	} else {
		dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
		dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
		amba_device_register(&exynos_pdma0_device, &iomem_resource);

		dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
		dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
		amba_device_register(&exynos_pdma1_device, &iomem_resource);

		dma_cap_set(DMA_MEMCPY, exynos_mdma_pdata.cap_mask);
		amba_device_register(&exynos_mdma_device, &iomem_resource);
	}

	if (soc_is_exynos5420()) {
		dma_cap_set(DMA_SLAVE, exynos_adma0_pdata.cap_mask);
		dma_cap_set(DMA_CYCLIC, exynos_adma0_pdata.cap_mask);
		amba_device_register(&exynos_adma0_device, &iomem_resource);
	}

	return 0;
}
static u32 exynos_usb_phy_set_clock(struct platform_device *pdev)
{
	struct clk *ref_clk;
	u32 refclk_freq = 0;

	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
		ref_clk = clk_get(&pdev->dev, "xusbxti");
	else
		ref_clk = clk_get(&pdev->dev, "ext_xtal");

	if (IS_ERR(ref_clk)) {
		dev_err(&pdev->dev, "Failed to get reference clock\n");
		return PTR_ERR(ref_clk);
	}

	if (soc_is_exynos4210()) {
		switch (clk_get_rate(ref_clk)) {
		case 12 * MHZ:
			refclk_freq = EXYNOS4210_CLKSEL_12M;
			break;
		case 48 * MHZ:
			refclk_freq = EXYNOS4210_CLKSEL_48M;
			break;
		case 24 * MHZ:
		default:
			/* default reference clock */
			refclk_freq = EXYNOS4210_CLKSEL_24M;
			break;
		}
	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {
		switch (clk_get_rate(ref_clk)) {
		case 96 * 100000:
			refclk_freq = EXYNOS4212_CLKSEL_9600K;
			break;
		case 10 * MHZ:
			refclk_freq = EXYNOS4212_CLKSEL_10M;
			break;
		case 12 * MHZ:
			refclk_freq = EXYNOS4212_CLKSEL_12M;
			break;
		case 192 * 100000:
			refclk_freq = EXYNOS4212_CLKSEL_19200K;
			break;
		case 20 * MHZ:
			refclk_freq = EXYNOS4212_CLKSEL_20M;
			break;
		case 24 * MHZ:
		default:
			/* default reference clock */
			refclk_freq = EXYNOS4212_CLKSEL_24M;
			break;
		}
	} else {
		switch (clk_get_rate(ref_clk)) {
		case 96 * 100000:
			refclk_freq = EXYNOS5_CLKSEL_9600K;
			break;
		case 10 * MHZ:
			refclk_freq = EXYNOS5_CLKSEL_10M;
			break;
		case 12 * MHZ:
			refclk_freq = EXYNOS5_CLKSEL_12M;
			break;
		case 192 * 100000:
			refclk_freq = EXYNOS5_CLKSEL_19200K;
			break;
		case 20 * MHZ:
			refclk_freq = EXYNOS5_CLKSEL_20M;
			break;
		case 50 * MHZ:
			refclk_freq = EXYNOS5_CLKSEL_50M;
			break;
		case 24 * MHZ:
		default:
			/* default reference clock */
			refclk_freq = EXYNOS5_CLKSEL_24M;
			break;
		}
	}
	clk_put(ref_clk);

	return refclk_freq;
}
int exynos4_check_usb_op(void)
{
	u32 phypwr;
	u32 op = 1;
	unsigned long flags;
	int ret;

	ret = clk_enable(phy_clk);
	if (ret)
		return 0;

	local_irq_save(flags);
	phypwr = readl(EXYNOS4_PHYPWR);

	/*If USB Device is power on,  */
	if (exynos_usb_device_phy_is_on()) {
		op = 1;
		goto done;
	} else if (!exynos4_usb_host_phy_is_on()) {
		op = 0;
		goto done;
	}

	/*If USB Device & Host is suspended,  */
	if (soc_is_exynos4210()) {
		if (phypwr & (PHY1_STD_FORCE_SUSPEND
			| EXYNOS4210_HSIC0_FORCE_SUSPEND
			| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
			/* HSIC LPA: LPA USB phy retention reume call the usb
			* reset resume, so we should let CP to HSIC L3 mode. */
			set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
			writel(readl(EXYNOS4_PHYPWR)
				| PHY1_STD_ANALOG_POWERDOWN,
				EXYNOS4_PHYPWR);
			writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);

			op = 0;
		}
	} else {
		if (phypwr & (PHY1_STD_FORCE_SUSPEND
			| EXYNOS4212_HSIC0_FORCE_SUSPEND
			| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
			/* HSIC LPA: LPA USB phy retention reume call the usb
			* reset resume, so we should let CP to HSIC L3 mode. */
			set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
			/* unset to normal of Host */
			writel(readl(EXYNOS4_PHYPWR)
				| PHY1_STD_ANALOG_POWERDOWN
				| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
				| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
				EXYNOS4_PHYPWR);
			/* unset to normal of Device */
			writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
					EXYNOS4_PHYPWR);

			exynos_usb_phy_control(USB_PHY
				| USB_PHY_HSIC0
				| USB_PHY_HSIC1,
				PHY_DISABLE);

			op = 0;
			usb_phy_control.lpa_entered = 1;
		}
	}
done:
	local_irq_restore(flags);
	clk_disable(phy_clk);

	return op;
}