void s3c_adc_phy_init(void)
{
u32 reg;
if (soc_is_exynos5250() || soc_is_exynos4415() ||
soc_is_exynos3470() || soc_is_exynos3250()) {
reg = __raw_readl(EXYNOS5250_ADC_PHY_CONTROL);
reg |= EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5250_ADC_PHY_CONTROL);
} else if (soc_is_exynos5410() || soc_is_exynos5420()) {
reg = __raw_readl(EXYNOS5410_ADC_PHY_CONTROL);
reg |= EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5410_ADC_PHY_CONTROL);
} else if (soc_is_exynos5260()) {
/* ADC phy select */
reg = readl(EXYNOS5260_SYSCON_PERI_PHY_SELECT);
if (reg & EXYNOS5260_SYSCON_PERI_PHY_SELECT_ISP_ONLY)
reg &= ~(EXYNOS5260_SYSCON_PERI_PHY_SELECT_ISP_ONLY);
writel(reg, EXYNOS5260_SYSCON_PERI_PHY_SELECT);
reg = __raw_readl(EXYNOS5260_ADC_PHY_CONTROL);
reg |= EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5260_ADC_PHY_CONTROL);
}
}
void __init exynos5_hs_i2c0_set_platdata(struct exynos5_platform_i2c *pd)
{
struct exynos5_platform_i2c *npd;
if (!pd) {
pd = &default_hs_i2c_data;
pd->bus_number = 4;
pd->speed_mode = HSI2C_HIGH_SPD;
}
npd = kmemdup(pd, sizeof(struct exynos5_platform_i2c), GFP_KERNEL);
if (!npd) {
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
return;
}
if (!npd->cfg_gpio)
npd->cfg_gpio = exynos5_hs_i2c0_cfg_gpio;
exynos5_device_hs_i2c0.dev.platform_data = npd;
if (soc_is_exynos5410()) {
exynos5_device_hs_i2c0.resource[0].start = EXYNOS5410_PA_HSIIC(0);
exynos5_device_hs_i2c0.resource[0].end = EXYNOS5410_PA_HSIIC(0) + SZ_4K - 1;
exynos5_device_hs_i2c0.resource[1].start = IRQ_IIC4;
exynos5_device_hs_i2c0.resource[1].end = IRQ_IIC4;
} else if (soc_is_exynos5420()) {
exynos5_device_hs_i2c0.resource[0].start = EXYNOS5420_PA_HSIIC0;
exynos5_device_hs_i2c0.resource[0].end = EXYNOS5420_PA_HSIIC0 + SZ_4K - 1;
exynos5_device_hs_i2c0.resource[1].start = IRQ_IIC4;
exynos5_device_hs_i2c0.resource[1].end = IRQ_IIC4;
}
}
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
if (soc_is_exynos5250())
s3c_gpio_cfgall_range(EXYNOS5_GPB3(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5260())
s3c_gpio_cfgall_range(EXYNOS5260_GPB4(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5410())
s3c_gpio_cfgall_range(EXYNOS5410_GPB3(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5420())
s3c_gpio_cfgall_range(EXYNOS5420_GPB3(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos3250())
s3c_gpio_cfgall_range(EXYNOS3_GPD1(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else /* EXYNOS4210, EXYNOS4212, and EXYNOS4412 */
s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
static void exynos_sfr_save(unsigned int i)
{
struct dw_mci *host = dw_mci_lpa_host[i];
dw_mci_save_sfr[i][0] = __raw_readl(host->regs + DWMCI_CTRL);
dw_mci_save_sfr[i][1] = __raw_readl(host->regs + DWMCI_PWREN);
dw_mci_save_sfr[i][2] = __raw_readl(host->regs + DWMCI_CLKDIV);
dw_mci_save_sfr[i][3] = __raw_readl(host->regs + DWMCI_CLKSRC);
dw_mci_save_sfr[i][4] = __raw_readl(host->regs + DWMCI_CLKENA);
dw_mci_save_sfr[i][5] = __raw_readl(host->regs + DWMCI_TMOUT);
dw_mci_save_sfr[i][6] = __raw_readl(host->regs + DWMCI_CTYPE);
dw_mci_save_sfr[i][7] = __raw_readl(host->regs + DWMCI_INTMASK);
dw_mci_save_sfr[i][8] = __raw_readl(host->regs + DWMCI_FIFOTH);
dw_mci_save_sfr[i][9] = __raw_readl(host->regs + DWMCI_UHS_REG);
dw_mci_save_sfr[i][10] = __raw_readl(host->regs + DWMCI_BMOD);
dw_mci_save_sfr[i][11] = __raw_readl(host->regs + DWMCI_PLDMND);
dw_mci_save_sfr[i][12] = __raw_readl(host->regs + DWMCI_DBADDR);
dw_mci_save_sfr[i][13] = __raw_readl(host->regs + DWMCI_IDINTEN);
dw_mci_save_sfr[i][14] = __raw_readl(host->regs + DWMCI_CLKSEL);
dw_mci_save_sfr[i][15] = __raw_readl(host->regs + DWMCI_CDTHRCTL);
if (soc_is_exynos3250() || soc_is_exynos4415() ||
soc_is_exynos5420() || soc_is_exynos5260() || soc_is_exynos3470()) {
dw_mci_save_sfr[i][16] = __raw_readl(host->regs +
DWMCI_DDR200_RDDQS_EN + 0x70);
dw_mci_save_sfr[i][17] = __raw_readl(host->regs +
DWMCI_DDR200_DLINE_CTRL + 0x70);
} else {
dw_mci_save_sfr[i][16] = __raw_readl(host->regs +
DWMCI_DDR200_RDDQS_EN);
dw_mci_save_sfr[i][17] = __raw_readl(host->regs +
DWMCI_DDR200_DLINE_CTRL);
}
}
void __init exynos_dwmci_set_platdata(struct dw_mci_board *pd, u32 slot_id)
{
struct dw_mci_board *npd = NULL;
if ((soc_is_exynos4210()) || soc_is_exynos4212() ||
soc_is_exynos4412()) {
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
&exynos4_device_dwmci);
} else if (soc_is_exynos5250() || soc_is_exynos5410() ||
soc_is_exynos5420()) {
if (slot_id < ARRAY_SIZE(exynos5_dwmci_devs))
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
exynos5_dwmci_devs[slot_id]);
else
pr_err("%s: slot %d is not supported\n", __func__,
slot_id);
}
if (!npd)
return;
if (!npd->init)
npd->init = exynos_dwmci_init;
if (!npd->get_bus_wd)
npd->get_bus_wd = exynos_dwmci_get_bus_wd;
if (!npd->set_io_timing)
npd->set_io_timing = exynos_dwmci_set_io_timing;
if (!npd->get_ocr)
npd->get_ocr = exynos_dwmci_get_ocr;
if (!npd->clk_tbl)
npd->clk_tbl = exynos_dwmci_clk_rates;
if (!npd->cfg_smu)
npd->cfg_smu = exynos_dwmci_cfg_smu;
}
void change_all_power_base_to(unsigned int cluster)
{
int i;
int offset = 0;
if (!soc_is_exynos5410() && !soc_is_exynos5420())
return;
if (soc_is_exynos5410()) {
if (samsung_rev() < EXYNOS5410_REV_1_0) {
if (cluster == 0)
offset = 4;
} else {
if (cluster != 0)
offset = 4;
}
} else {
if (cluster)
offset = 4;
}
for (i = 0; i < 4; i++) {
cpu_boot_info[i].power_base =
EXYNOS_ARM_CORE_CONFIGURATION(offset + i);
}
}
/*
* TMU treats temperature as a mapped temperature code.
* The temperature is converted differently depending on the calibration type.
*/
static int temp_to_code(struct exynos_tmu_data *data, u8 temp, int id)
{
struct exynos_tmu_platform_data *pdata = data->pdata;
int temp_code;
int fuse_id;
if (data->soc == SOC_ARCH_EXYNOS4)
/* temp should range between 25 and 125 */
if (temp < 25 || temp > 125) {
temp_code = -EINVAL;
goto out;
}
if (soc_is_exynos5420()) {
switch (id) {
case 0:
fuse_id = 0;
break;
case 1:
fuse_id = 1;
break;
case 2:
fuse_id = 3;
break;
case 3:
fuse_id = 4;
break;
case 4:
fuse_id = 2;
break;
default:
pr_err("unknown sensor id on Exynos5420\n");
BUG_ON(1);
break;
}
} else {
fuse_id = id;
}
switch (pdata->cal_type) {
case TYPE_TWO_POINT_TRIMMING:
temp_code = (temp - 25) *
(data->temp_error2[fuse_id] - data->temp_error1[fuse_id]) /
(85 - 25) + data->temp_error1[fuse_id];
break;
case TYPE_ONE_POINT_TRIMMING:
temp_code = temp + data->temp_error1[fuse_id] - 25;
break;
default:
temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
break;
}
out:
return temp_code;
}
static inline void __iomem *cpu_boot_reg(int cpu)
{
void __iomem *boot_reg;
boot_reg = cpu_boot_reg_base();
if (soc_is_exynos4412())
boot_reg += 4*cpu;
else if (soc_is_exynos5420())
boot_reg += 4;
return boot_reg;
}
static inline void __iomem *cpu_boot_reg(int cpu)
{
void __iomem *boot_reg;
boot_reg = cpu_boot_reg_base();
if (!boot_reg)
return ERR_PTR(-ENODEV);
if (soc_is_exynos4412())
boot_reg += 4*cpu;
else if (soc_is_exynos5420() || soc_is_exynos5800())
boot_reg += 4;
return boot_reg;
}
static int exynos_spdif_cfg_gpio(struct platform_device *pdev)
{
/* configure GPIO for SPDIF port */
if (soc_is_exynos5250())
s3c_gpio_cfgpin_range(EXYNOS5_GPB1(0), 2, S3C_GPIO_SFN(4));
else if (soc_is_exynos5410())
s3c_gpio_cfgpin_range(EXYNOS5410_GPB1(0), 2, S3C_GPIO_SFN(4));
else if (soc_is_exynos5420())
s3c_gpio_cfgpin_range(EXYNOS5420_GPB1(0), 2, S3C_GPIO_SFN(4));
else if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
return 0;
}
void exynos5_hs_i2c1_cfg_gpio(struct platform_device *dev)
{
if (soc_is_exynos5250())
s3c_gpio_cfgall_range(EXYNOS5_GPB3(2), 2,
S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5410())
s3c_gpio_cfgall_range(EXYNOS5410_GPA2(2), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5420())
s3c_gpio_cfgall_range(EXYNOS5420_GPA2(2), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else
pr_err("failed to configure gpio for hs-i2c1\n");
}
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
if (soc_is_exynos5250())
s3c_gpio_cfgall_range(EXYNOS5_GPB3(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5410())
s3c_gpio_cfgall_range(EXYNOS5410_GPB3(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5420())
s3c_gpio_cfgall_range(EXYNOS5420_GPB3(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else /* EXYNOS4210, EXYNOS4212, and EXYNOS4412 */
s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
if (soc_is_exynos5420()) {
s5p_gpio_set_drvstr(EXYNOS5_GPB3(0), S5P_GPIO_DRVSTR_LV4);
s5p_gpio_set_drvstr(EXYNOS5_GPB3(1), S5P_GPIO_DRVSTR_LV4);
}
}
void __init exynos5_hs_i2c3_set_platdata(struct exynos5_platform_i2c *pd)
{
struct exynos5_platform_i2c *npd;
if (!pd) {
pd = &default_hs_i2c_data;
if (soc_is_exynos5260())
pd->bus_number = 3;
else
pd->bus_number = 7;
pd->speed_mode = HSI2C_FAST_SPD;
}
if (soc_is_exynos5260())
pd->fifo_size = 16;
else
pd->fifo_size = 64;
npd = kmemdup(pd, sizeof(struct exynos5_platform_i2c), GFP_KERNEL);
if (!npd) {
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
return;
}
if (!npd->cfg_gpio)
npd->cfg_gpio = exynos5_hs_i2c3_cfg_gpio;
exynos5_device_hs_i2c3.dev.platform_data = npd;
if (soc_is_exynos5410()) {
exynos5_device_hs_i2c3.resource[0].start = EXYNOS5410_PA_HSIIC(3);
exynos5_device_hs_i2c3.resource[0].end = EXYNOS5410_PA_HSIIC(3) + SZ_4K - 1;
exynos5_device_hs_i2c3.resource[1].start = IRQ_IIC7;
exynos5_device_hs_i2c3.resource[1].end = IRQ_IIC7;
} else if (soc_is_exynos5420()) {
exynos5_device_hs_i2c3.resource[0].start = EXYNOS5420_PA_HSIIC3;
exynos5_device_hs_i2c3.resource[0].end = EXYNOS5420_PA_HSIIC3 + SZ_4K - 1;
exynos5_device_hs_i2c3.resource[1].start = IRQ_IIC7;
exynos5_device_hs_i2c3.resource[1].end = IRQ_IIC7;
} else if (soc_is_exynos5260()) {
exynos5_device_hs_i2c3.resource[0].start = EXYNOS5260_PA_HSIIC(3);
exynos5_device_hs_i2c3.resource[0].end = EXYNOS5260_PA_HSIIC(3) + SZ_4K - 1;
exynos5_device_hs_i2c3.resource[1].start = IRQ_IIC3;
exynos5_device_hs_i2c3.resource[1].end = IRQ_IIC3;
}
}
static void exynos_dwmci_cfg_smu(void *data, u32 action)
{
struct dw_mci *host = (struct dw_mci *)data;
if (!soc_is_exynos5420() || action != 0)
return;
/* bypass mode */
if (host->pdata->ch_num != 2) {
__raw_writel(0, host->regs + DWMCI_MPSBEGIN0);
__raw_writel(0xFFFFFFFF, host->regs + DWMCI_MPSEND0);
__raw_writel(DWMCI_MPSCTRL_SECURE_READ_BIT |
DWMCI_MPSCTRL_SECURE_WRITE_BIT |
DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT |
DWMCI_MPSCTRL_VALID, host->regs + DWMCI_MPSCTRL0);
}
}
static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
struct exynos_gpio_cfg exynos4_cfg[3] = {
{ EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(2) }
};
struct exynos_gpio_cfg exynos5_cfg[3] = {
{ EXYNOS5_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
};
struct exynos_gpio_cfg exynos5410_cfg[3] = {
{ EXYNOS5410_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS5410_GPB0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS5410_GPB1(0), 5, S3C_GPIO_SFN(2) }
};
struct exynos_gpio_cfg exynos5420_cfg[3] = {
{ EXYNOS5420_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS5420_GPB0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS5420_GPB1(0), 5, S3C_GPIO_SFN(2) }
};
if (pdev->id < 0 || pdev->id > 2) {
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
if (soc_is_exynos5250())
s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,
exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);
else if (soc_is_exynos5410())
s3c_gpio_cfgpin_range(exynos5410_cfg[pdev->id].addr,
exynos5410_cfg[pdev->id].num, exynos5410_cfg[pdev->id].bit);
else if (soc_is_exynos5420())
s3c_gpio_cfgpin_range(exynos5420_cfg[pdev->id].addr,
exynos5420_cfg[pdev->id].num, exynos5420_cfg[pdev->id].bit);
else if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,
exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);
return 0;
}
void s3c_adc_phy_exit(void)
{
u32 reg;
if (soc_is_exynos5250() || soc_is_exynos4415() ||
soc_is_exynos3470() || soc_is_exynos3250()) {
reg = __raw_readl(EXYNOS5250_ADC_PHY_CONTROL);
reg &= ~EXYNOS5_ADC_PHY_ENABLE;
reg |= EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5250_ADC_PHY_CONTROL);
} else if (soc_is_exynos5410() || soc_is_exynos5420()) {
reg = __raw_readl(EXYNOS5410_ADC_PHY_CONTROL);
reg &= ~EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5410_ADC_PHY_CONTROL);
} else if (soc_is_exynos5260()) {
reg = __raw_readl(EXYNOS5260_ADC_PHY_CONTROL);
reg &= ~EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5260_ADC_PHY_CONTROL);
}
}
void exynos_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int i;
if (soc_is_exynos5250())
exynos5_init_pmu();
if (soc_is_exynos5420())
exynos_set_core_flag();
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
__raw_writel(exynos_pmu_config[i].val[mode],
exynos_pmu_config[i].reg);
if (soc_is_exynos4412()) {
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
__raw_writel(exynos4412_pmu_config[i].val[mode],
exynos4412_pmu_config[i].reg);
}
}
/* sysfs interface : /sys/devices/platform/exynos5-tmu/curr_temp */
static ssize_t
exynos_thermal_curr_temp(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct exynos_tmu_data *data = th_zone->sensor_conf->private_data;
unsigned long temp[EXYNOS_TMU_COUNT];
int i, len = 0;
if (!(soc_is_exynos5410() || soc_is_exynos5420() || soc_is_exynos5260()))
return -EPERM;
if (EXYNOS_TMU_COUNT < 4)
return -EPERM;
mutex_lock(&data->lock);
clk_enable(data->clk);
for (i = 0; i < EXYNOS_TMU_COUNT; i++) {
u8 temp_code = readb(data->base[i] + EXYNOS_TMU_REG_CURRENT_TEMP);
if (temp_code == 0xff)
temp[i] = 0;
else
temp[i] = code_to_temp(data, temp_code, i) * 10;
}
clk_disable(data->clk);
mutex_unlock(&data->lock);
len += sprintf(&buf[len], "%ld,", temp[0]);
len += sprintf(&buf[len], "%ld,", temp[1]);
len += sprintf(&buf[len], "%ld,", temp[2]);
len += sprintf(&buf[len], "%ld,", temp[3]);
len += sprintf(&buf[len], "%ld\n", temp[4]);
return len;
}
static int __init exynos_dma_init(void)
{
if (of_have_populated_dt())
return 0;
if (soc_is_exynos4210()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
} else if (soc_is_exynos4415()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4415_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos4415_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4415_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos4415_pdma1_peri;
} else if (soc_is_exynos5250()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5250_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5250_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
} else if (soc_is_exynos5410()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5410_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos5410_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5410_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos5410_pdma1_peri;
} else if (soc_is_exynos5420()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5420_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos5420_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5420_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos5420_pdma1_peri;
exynos_adma0_pdata.nr_valid_peri =
ARRAY_SIZE(adma0_peri);
exynos_adma0_pdata.peri_id = adma0_peri;
} else if (soc_is_exynos5260()) {
exynos5260_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5260_pdma0_peri);
exynos5260_pdma0_pdata.peri_id = exynos5260_pdma0_peri;
} else if (soc_is_exynos3470()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos3470_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos3470_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos3470_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos3470_pdma1_peri;
} else if (soc_is_exynos3250()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos3250_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos3250_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos3250_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos3250_pdma1_peri;
}
if (soc_is_exynos4210() || soc_is_exynos4212() ||
soc_is_exynos4412() || soc_is_exynos3470()) {
exynos_pdma0_device.res.start = EXYNOS4_PA_PDMA0;
exynos_pdma0_device.res.end = EXYNOS4_PA_PDMA0 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS4_IRQ_PDMA0;
exynos_pdma1_device.res.start = EXYNOS4_PA_PDMA1;
exynos_pdma1_device.res.end = EXYNOS4_PA_PDMA1 + SZ_4K;
exynos_pdma1_device.irq[0] = EXYNOS4_IRQ_PDMA1;
exynos_mdma_device.res.start = EXYNOS4_PA_MDMA1;
exynos_mdma_device.res.end = EXYNOS4_PA_MDMA1 + SZ_4K;
exynos_mdma_device.irq[0] = EXYNOS4_IRQ_MDMA1;
} else if (soc_is_exynos5410() || soc_is_exynos5420()) {
exynos_mdma_device.res.start = EXYNOS5_PA_MDMA0;
exynos_mdma_device.res.end = EXYNOS5_PA_MDMA0 + SZ_4K;
exynos_mdma_device.irq[0] = EXYNOS5_IRQ_MDMA0;
} else if (soc_is_exynos5260()) {
exynos5260_pdma0_device.res.start = EXYNOS5260_PA_PDMA0;
exynos5260_pdma0_device.res.end = EXYNOS5260_PA_PDMA0 + SZ_4K;
exynos5260_pdma0_device.irq[0] = EXYNOS5260_IRQ_PDMA0;
exynos5260_mdma_device.res.start = EXYNOS5260_PA_NS_MDMA0;
exynos5260_mdma_device.res.end = EXYNOS5260_PA_NS_MDMA0 + SZ_4K;
exynos5260_mdma_device.irq[0] = EXYNOS5260_IRQ_MDMA_1;
exynos5260_adma_device.res.start = EXYNOS5260_PA_ADMA0;
exynos5260_adma_device.res.end = EXYNOS5260_PA_ADMA0 + SZ_4K;
exynos5260_adma_device.irq[0] = EXYNOS5260_IRQ_ADMA;
} else if (soc_is_exynos4415()) {
exynos_pdma0_device.res.start = EXYNOS4_PA_PDMA0;
exynos_pdma0_device.res.end = EXYNOS4_PA_PDMA0 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS4_IRQ_PDMA0;
exynos_pdma1_device.res.start = EXYNOS4_PA_PDMA1;
exynos_pdma1_device.res.end = EXYNOS4_PA_PDMA1 + SZ_4K;
exynos_pdma1_device.irq[0] = EXYNOS4_IRQ_PDMA1;
exynos_mdma_device.res.start = EXYNOS4_PA_MDMA1;
exynos_mdma_device.res.end = EXYNOS4_PA_MDMA1 + SZ_4K;
exynos_mdma_device.irq[0] = EXYNOS4_IRQ_MDMA1;
} else if (soc_is_exynos3250()) {
exynos_pdma0_device.res.start = EXYNOS3_PA_PDMA0;
exynos_pdma0_device.res.end = EXYNOS3_PA_PDMA0 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS3_IRQ_PDMA0;
exynos_pdma1_device.res.start = EXYNOS3_PA_PDMA1;
exynos_pdma1_device.res.end = EXYNOS3_PA_PDMA1 + SZ_4K;
exynos_pdma1_device.irq[0] = EXYNOS3_IRQ_PDMA1;
}
if (soc_is_exynos5260()) {
dma_cap_set(DMA_SLAVE, exynos5260_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos5260_pdma0_pdata.cap_mask);
amba_device_register(&exynos5260_pdma0_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos5260_mdma_pdata.cap_mask);
amba_device_register(&exynos5260_mdma_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos5260_adma_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos5260_adma_pdata.cap_mask);
amba_device_register(&exynos5260_adma_device, &iomem_resource);
} else if (soc_is_exynos3250()) {
dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
amba_device_register(&exynos_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
amba_device_register(&exynos_pdma1_device, &iomem_resource);
} else {
dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
amba_device_register(&exynos_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
amba_device_register(&exynos_pdma1_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos_mdma_pdata.cap_mask);
amba_device_register(&exynos_mdma_device, &iomem_resource);
}
if (soc_is_exynos5420()) {
dma_cap_set(DMA_SLAVE, exynos_adma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_adma0_pdata.cap_mask);
amba_device_register(&exynos_adma0_device, &iomem_resource);
}
return 0;
}
static void exynos_dwmci_set_io_timing(void *data, unsigned int tuning, unsigned char timing)
{
struct dw_mci *host = (struct dw_mci *)data;
struct dw_mci_board *pdata = host->pdata;
struct dw_mci_clk *clk_tbl = pdata->clk_tbl;
u32 clksel, rddqs, dline;
u32 sclkin, cclkin;
unsigned char timing_org = timing;
if (timing > MMC_TIMING_MMC_HS200_DDR_ES) {
pr_err("%s: timing(%d): not suppored\n", __func__, timing);
return;
}
if (timing == MMC_TIMING_MMC_HS200_DDR_ES)
timing = MMC_TIMING_MMC_HS200_DDR;
sclkin = clk_tbl[timing].sclkin;
cclkin = clk_tbl[timing].cclkin;
rddqs = DWMCI_DDR200_RDDQS_EN_DEF;
dline = DWMCI_DDR200_DLINE_CTRL_DEF;
clksel = __raw_readl(host->regs + DWMCI_CLKSEL);
if (host->bus_hz != cclkin) {
host->bus_hz = cclkin;
host->current_speed = 0;
clk_set_rate(host->cclk, sclkin);
}
if (timing == MMC_TIMING_MMC_HS200_DDR) {
clksel = (pdata->ddr200_timing & 0xfffffff8) | pdata->clk_smpl;
if (!tuning) {
rddqs |= DWMCI_RDDQS_EN;
if (timing_org == MMC_TIMING_MMC_HS200_DDR_ES) {
rddqs |= DWMCI_RESP_RCLK_MODE;
}
#if defined(CONFIG_V1A) || defined(CONFIG_V2A) || defined(CONFIG_CHAGALL)
dline = DWMCI_FIFO_CLK_DELAY_CTRL(0x2) | DWMCI_RD_DQS_DELAY_CTRL(110);
#elif defined(CONFIG_N1A) || defined(CONFIG_N2A)
dline = DWMCI_FIFO_CLK_DELAY_CTRL(0x2) | DWMCI_RD_DQS_DELAY_CTRL(100);
#else
dline = DWMCI_FIFO_CLK_DELAY_CTRL(0x2) | DWMCI_RD_DQS_DELAY_CTRL(90);
#endif
host->quirks &= ~DW_MCI_QUIRK_NO_DETECT_EBIT;
}
} else if (timing == MMC_TIMING_MMC_HS200 ||
timing == MMC_TIMING_UHS_SDR104) {
clksel = (clksel & 0xfff8ffff) | (pdata->clk_drv << 16);
} else if (timing == MMC_TIMING_UHS_SDR50) {
clksel = (clksel & 0xfff8ffff) | (pdata->clk_drv << 16);
} else if (timing == MMC_TIMING_UHS_DDR50) {
clksel = pdata->ddr_timing;
} else {
clksel = pdata->sdr_timing;
}
__raw_writel(clksel, host->regs + DWMCI_CLKSEL);
if (soc_is_exynos5420()) {
__raw_writel(rddqs, host->regs + DWMCI_DDR200_RDDQS_EN + 0x70);
__raw_writel(dline, host->regs + DWMCI_DDR200_DLINE_CTRL + 0x70);
} else {
__raw_writel(rddqs, host->regs + DWMCI_DDR200_RDDQS_EN);
__raw_writel(dline, host->regs + DWMCI_DDR200_DLINE_CTRL);
}
}
static void exynos_sfr_restore(unsigned int i)
{
struct dw_mci *host = dw_mci_lpa_host[i];
int startbit_clear = false;
unsigned int cmd_status = 0;
unsigned long timeout = jiffies + msecs_to_jiffies(500);
/*
* To update clock configurations, CIU should be enabled.
*/
spin_lock(&host->cclk_lock);
dw_mci_ciu_clk_en(host);
spin_unlock(&host->cclk_lock);
__raw_writel(dw_mci_save_sfr[i][0], host->regs + DWMCI_CTRL);
__raw_writel(dw_mci_save_sfr[i][1], host->regs + DWMCI_PWREN);
__raw_writel(dw_mci_save_sfr[i][2], host->regs + DWMCI_CLKDIV);
__raw_writel(dw_mci_save_sfr[i][3], host->regs + DWMCI_CLKSRC);
__raw_writel(dw_mci_save_sfr[i][4], host->regs + DWMCI_CLKENA);
__raw_writel(dw_mci_save_sfr[i][5], host->regs + DWMCI_TMOUT);
__raw_writel(dw_mci_save_sfr[i][6], host->regs + DWMCI_CTYPE);
__raw_writel(dw_mci_save_sfr[i][7], host->regs + DWMCI_INTMASK);
__raw_writel(dw_mci_save_sfr[i][8], host->regs + DWMCI_FIFOTH);
__raw_writel(dw_mci_save_sfr[i][9], host->regs + DWMCI_UHS_REG);
__raw_writel(dw_mci_save_sfr[i][10], host->regs + DWMCI_BMOD);
__raw_writel(dw_mci_save_sfr[i][11], host->regs + DWMCI_PLDMND);
__raw_writel(dw_mci_save_sfr[i][12], host->regs + DWMCI_DBADDR);
__raw_writel(dw_mci_save_sfr[i][13], host->regs + DWMCI_IDINTEN);
__raw_writel(dw_mci_save_sfr[i][14], host->regs + DWMCI_CLKSEL);
__raw_writel(dw_mci_save_sfr[i][15], host->regs + DWMCI_CDTHRCTL);
if (soc_is_exynos3250() || soc_is_exynos4415() ||
soc_is_exynos5420() || soc_is_exynos5260() || soc_is_exynos3470()) {
__raw_writel(dw_mci_save_sfr[i][16], host->regs +
DWMCI_DDR200_RDDQS_EN + 0x70);
__raw_writel(dw_mci_save_sfr[i][17], host->regs +
DWMCI_DDR200_DLINE_CTRL + 0x70);
} else {
__raw_writel(dw_mci_save_sfr[i][16], host->regs +
DWMCI_DDR200_RDDQS_EN);
__raw_writel(dw_mci_save_sfr[i][17], host->regs +
DWMCI_DDR200_DLINE_CTRL);
}
__raw_writel(0, host->regs + DWMCI_CMDARG);
wmb();
#ifdef CONFIG_BCM4334
if (i == 1)
return;
#endif
__raw_writel((DWMCI_CMD_START | DWMCI_CMD_UPD_CLK | DWMCI_CMD_PRV_DAT_WAIT),
host->regs + DWMCI_CMD);
while (time_before(jiffies, timeout)) {
cmd_status = __raw_readl(host->regs + DWMCI_CMD);
if (!(cmd_status & DWMCI_CMD_START)) {
startbit_clear = true;
return;
}
}
if (startbit_clear == false)
dev_err(&host->dev, "CMD start bit stuck %02d\n", i);
}
static void exynos_dwmci_set_io_timing(void *data, unsigned int tuning,
unsigned char timing, struct mmc_host *mmc)
{
struct dw_mci *host = (struct dw_mci *)data;
struct dw_mci_board *pdata = host->pdata;
struct dw_mci_clk *clk_tbl = pdata->clk_tbl;
u32 clksel, rddqs, dline;
u32 sclkin, cclkin;
unsigned char timing_init = MMC_TIMING_INIT;
if (timing > MMC_TIMING_MMC_HS200_DDR) {
pr_err("%s: timing(%d): not suppored\n", __func__, timing);
return;
}
sclkin = clk_tbl[timing].sclkin;
cclkin = clk_tbl[timing].cclkin;
if (timing == MMC_TIMING_LEGACY &&
pdata->misc_flag & DW_MMC_MISC_LOW_FREQ_HOOK) {
if (mmc == NULL || (mmc && mmc->ios.clock <= mmc->f_init)) {
sclkin = clk_tbl[timing_init].sclkin;
cclkin = clk_tbl[timing_init].cclkin;
}
}
rddqs = DWMCI_DDR200_RDDQS_EN_DEF;
dline = DWMCI_DDR200_DLINE_CTRL_DEF;
clksel = __raw_readl(host->regs + DWMCI_CLKSEL);
if (host->bus_hz != cclkin) {
host->bus_hz = cclkin;
host->current_speed = 0;
if (host->cclk2)
clk_set_rate(host->cclk2, sclkin);
clk_set_rate(host->cclk, sclkin);
}
if (timing == MMC_TIMING_MMC_HS200_DDR) {
clksel = (pdata->ddr200_timing & 0xfffffff8) | pdata->clk_smpl;
if (pdata->is_fine_tuned)
clksel |= BIT(6);
if (!tuning) {
rddqs |= DWMCI_RDDQS_EN;
if (host->pdata->delay_line)
dline = DWMCI_FIFO_CLK_DELAY_CTRL(0x2) |
DWMCI_RD_DQS_DELAY_CTRL(host->pdata->delay_line);
else
dline = DWMCI_FIFO_CLK_DELAY_CTRL(0x2) |
DWMCI_RD_DQS_DELAY_CTRL(90);
host->quirks &= ~DW_MCI_QUIRK_NO_DETECT_EBIT;
}
} else if (timing == MMC_TIMING_MMC_HS200 ||
timing == MMC_TIMING_UHS_SDR104) {
clksel = (clksel & 0xfff8ffff) | (pdata->clk_drv << 16);
} else if (timing == MMC_TIMING_UHS_SDR50) {
clksel = (clksel & 0xfff8ffff) | (pdata->clk_drv << 16);
} else if (timing == MMC_TIMING_UHS_DDR50) {
clksel = pdata->ddr_timing;
} else {
clksel = pdata->sdr_timing;
}
__raw_writel(clksel, host->regs + DWMCI_CLKSEL);
if (soc_is_exynos3250() || soc_is_exynos4415() ||
soc_is_exynos5420() || soc_is_exynos5260() || soc_is_exynos3470()) {
__raw_writel(rddqs, host->regs + DWMCI_DDR200_RDDQS_EN + 0x70);
__raw_writel(dline, host->regs + DWMCI_DDR200_DLINE_CTRL + 0x70);
if (timing == MMC_TIMING_MMC_HS200_DDR)
__raw_writel(0x1, host->regs + DWMCI_DDR200_ASYNC_FIFO_CTRL + 0x70);
} else {
__raw_writel(rddqs, host->regs + DWMCI_DDR200_RDDQS_EN);
__raw_writel(dline, host->regs + DWMCI_DDR200_DLINE_CTRL);
if (timing == MMC_TIMING_MMC_HS200_DDR)
__raw_writel(0x1, host->regs + DWMCI_DDR200_ASYNC_FIFO_CTRL);
}
}
/*
* Calculate a temperature value from a temperature code.
* The unit of the temperature is degree Celsius.
*/
static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code, int id)
{
struct exynos_tmu_platform_data *pdata = data->pdata;
int min, max, temp;
int fuse_id;
if (data->soc == SOC_ARCH_EXYNOS4) {
min = 75;
max = 175;
} else {
min = 31;
max = 146;
}
if (soc_is_exynos5420()) {
switch (id) {
case 0:
fuse_id = 0;
break;
case 1:
fuse_id = 1;
break;
case 2:
fuse_id = 3;
break;
case 3:
fuse_id = 4;
break;
case 4:
fuse_id = 2;
break;
default:
pr_err("unknown sensor id on Exynos5420\n");
BUG_ON(1);
break;
}
} else {
fuse_id = id;
}
/* temp_code should range between min and max */
if (temp_code < min || temp_code > max) {
temp = -ENODATA;
goto out;
}
switch (pdata->cal_type) {
case TYPE_TWO_POINT_TRIMMING:
temp = (temp_code - data->temp_error1[fuse_id]) * (85 - 25) /
(data->temp_error2[fuse_id] - data->temp_error1[fuse_id]) + 25;
break;
case TYPE_ONE_POINT_TRIMMING:
temp = temp_code - data->temp_error1[fuse_id] + 25;
break;
default:
temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
break;
}
out:
return temp;
}
static int exynos_tmu_read(struct exynos_tmu_data *data)
{
u8 temp_code;
int temp, i, max = INT_MIN, min = INT_MAX, gpu_temp = 0;
#ifdef CONFIG_ARM_EXYNOS5410_BUS_DEVFREQ
enum tmu_noti_state_t cur_state;
#endif
int alltemp[EXYNOS_TMU_COUNT] = {0,};
if (!th_zone || !th_zone->therm_dev)
return -EPERM;
mutex_lock(&data->lock);
clk_enable(data->clk);
for (i = 0; i < EXYNOS_TMU_COUNT; i++) {
temp_code = readb(data->base[i] + EXYNOS_TMU_REG_CURRENT_TEMP);
temp = code_to_temp(data, temp_code, i);
if (temp < 0)
temp = 0;
alltemp[i] = temp;
if (temp > max)
max = temp;
if (temp < min)
min = temp;
if (soc_is_exynos5420() && i == EXYNOS_GPU_NUMBER)
gpu_temp = temp;
}
#ifdef CONFIG_SOC_EXYNOS5260
if (alltemp[EXYNOS_GPU0_NUMBER] > alltemp[EXYNOS_GPU1_NUMBER])
gpu_temp = alltemp[EXYNOS_GPU0_NUMBER];
else
gpu_temp = alltemp[EXYNOS_GPU1_NUMBER];
#endif
clk_disable(data->clk);
mutex_unlock(&data->lock);
#ifdef CONFIG_ARM_EXYNOS5410_BUS_DEVFREQ
if (min <= COLD_TEMP)
cur_state = TMU_COLD;
if (max >= HOT_110)
cur_state = TMU_110;
else if (max > HOT_95 && max < HOT_110)
cur_state = TMU_109;
else if (max <= HOT_95)
cur_state = TMU_95;
if (cur_state >= HOT_95)
pr_info("[TMU] POLLING: temp=%d, cpu=%d, int=%d, mif=%d, hot_event(for aref)=%d\n",
max, g_cpufreq, g_intfreq, g_miffreq, cur_state);
g_count++;
/* to probe thermal run away caused by fimc-is */
if ((max >= 112 && tmu_old_state == TMU_110)
&& g_cam_err_count && g_intfreq == 800000) {
cur_state = TMU_111;
}
exynos_tmu_call_notifier(cur_state);
#endif
if (soc_is_exynos5420()) {
/* check temperature state */
exynos_check_tmu_noti_state(min, max);
exynos_check_gpu_noti_state(gpu_temp);
#ifdef CONFIG_ARM_EXYNOS5420_BUS_DEVFREQ
if (!check_mif_probed())
goto out;
#endif
exynos_check_mif_noti_state(max);
}
if (soc_is_exynos5260()) {
exynos_check_tmu_noti_state(min, max);
exynos_check_gpu_noti_state(gpu_temp);
exynos_check_mif_noti_state(max);
}
#ifdef CONFIG_ARM_EXYNOS5420_BUS_DEVFREQ
out:
#endif
th_zone->therm_dev->last_temperature = max * MCELSIUS;
DTM_DBG("[TMU] TMU0 = %d, TMU1 = %d, TMU2 = %d, TMU3 = %d, TMU4 = %d ------- CPU : %d , GPU : %d\n",
alltemp[0], alltemp[1], alltemp[2], alltemp[3], alltemp[4], max, gpu_temp);
return max;
}
static int exynos_power_up_cpu(unsigned int cpu)
{
unsigned int timeout;
unsigned int val;
void __iomem *power_base;
#ifndef CONFIG_EXYNOS5_MP
unsigned int cluster = (read_cpuid_mpidr() >> 8) & 0xf;
#endif
unsigned int lpe_bits, lpe_bits_status, enabled = 0;
power_base = cpu_boot_info[cpu].power_base;
if (power_base == 0)
return -EPERM;
val = __raw_readl(power_base + 0x4);
if (soc_is_exynos5260()) {
if (val & 0x40000)
enabled = 1;
else {
val = __raw_readl(power_base + 0x8);
if (val & EXYNOS5_USE_SC_COUNTER) {
val &= ~EXYNOS5_USE_SC_COUNTER;
val |= EXYNOS5_USE_SC_FEEDBACK;
__raw_writel(val, power_base + 0x8);
}
lpe_bits = 0x000F000F;
lpe_bits_status = 0x4000F;
#ifndef CONFIG_ARM_TRUSTZONE
__raw_writel(0, cpu_boot_info[cpu].boot_base);
#endif
}
} else {
if (val & EXYNOS_CORE_LOCAL_PWR_EN)
enabled = 1;
else {
lpe_bits = EXYNOS_CORE_LOCAL_PWR_EN;
lpe_bits_status = EXYNOS_CORE_LOCAL_PWR_EN;
}
}
if (!enabled) {
__raw_writel(lpe_bits, power_base);
/* wait max 10 ms until cpu is on */
timeout = 10;
while (timeout) {
val = __raw_readl(power_base + 0x4);
if ((val & lpe_bits) ==
lpe_bits_status)
break;
mdelay(1);
timeout--;
}
if (timeout == 0) {
printk(KERN_ERR "cpu%d power up failed", cpu);
return -ETIMEDOUT;
}
}
#ifdef CONFIG_EXYNOS5_MP
if (cpu < 4) {
#else
if (cluster) {
#endif
while(!__raw_readl(EXYNOS_PMU_SPARE2))
udelay(10);
udelay(10);
if (soc_is_exynos5260()) {
val = __raw_readl(power_base + 0x4);
val |= (0xf << 8);
__raw_writel(val, power_base + 0x4);
pr_debug("cpu%d: SWRESEET\n", cpu);
__raw_writel((0x1 << 1), power_base + 0xc);
} else {
printk(KERN_DEBUG "cpu%d: SWRESET\n", cpu);
val = ((1 << 20) | (1 << 8)) << cpu;
__raw_writel(val, EXYNOS_SWRESET);
}
}
return 0;
}
#else
#error "exynos_power_up_cpu() does not defined"
#endif
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
int ret;
/*
* Set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
#ifdef CONFIG_WATCHDOG
if (soc_is_exynos5250())
watchdog_save();
#endif
#ifdef CONFIG_SOC_EXYNOS4415
__raw_writel(0x0, cpu_boot_info[cpu].boot_base);
#endif
ret = exynos_power_up_cpu(cpu);
if (ret) {
spin_unlock(&boot_lock);
return ret;
}
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
*
* Note that "pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
write_pen_release(cpu_logical_map(cpu));
/*
* Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
#ifdef CONFIG_ARM_TRUSTZONE
if (soc_is_exynos4210() || soc_is_exynos4212() ||
soc_is_exynos5250())
exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
else if (soc_is_exynos4412() || soc_is_exynos4415())
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
#endif
__raw_writel(virt_to_phys(exynos4_secondary_startup),
cpu_boot_info[cpu].boot_base);
#ifdef CONFIG_WATCHDOG
if (soc_is_exynos5250())
watchdog_restore();
#endif
if (soc_is_exynos3250() || soc_is_exynos3470() ||
soc_is_exynos5410() || soc_is_exynos5420() ||
soc_is_exynos5260())
dsb_sev();
else
arm_send_ping_ipi(cpu);
if (pen_release == -1)
break;
udelay(10);
}
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
static int __init exynos_pmu_init(void)
{
unsigned int value;
exynos_pmu_config = exynos4210_pmu_config;
if (soc_is_exynos4210()) {
exynos_pmu_config = exynos4210_pmu_config;
pr_info("EXYNOS4210 PMU Initialize\n");
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_pmu_config = exynos4x12_pmu_config;
pr_info("EXYNOS4x12 PMU Initialize\n");
} else if (soc_is_exynos5250()) {
exynos5250_disable_isp();
exynos_pmu_config = exynos5250_pmu_config;
pm_power_off = exynos5_power_off;
pr_info("EXYNOS5250 PMU Initialize\n");
} else if (soc_is_exynos5420()) {
__raw_writel(0xfffff, EXYNOS5_XXTI_DURATION3);
/* Enable USE_STANDBY_WFI for all CORE */
__raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
S5P_CENTRAL_SEQ_OPTION);
value = __raw_readl(EXYNOS_L2_OPTION(0));
value &= ~EXYNOS5_USE_RETENTION;
__raw_writel(value, EXYNOS_L2_OPTION(0));
value = __raw_readl(EXYNOS_L2_OPTION(1));
value &= ~EXYNOS5_USE_RETENTION;
__raw_writel(value, EXYNOS_L2_OPTION(1));
/*
* If L2_COMMON is turned off, clocks related to ATB async
* bridge are gated. Thus, when ISP power is gated, LPI
* may get stuck.
*/
value = __raw_readl(EXYNOS5420_LPI_MASK);
value |= EXYNOS5420_ATB_ISP_ARM;
__raw_writel(value, EXYNOS5420_LPI_MASK);
value = __raw_readl(EXYNOS5420_LPI_MASK1);
value |= EXYNOS5420_ATB_KFC;
__raw_writel(value, EXYNOS5420_LPI_MASK1);
/* Prevent issue of new bus request from L2 memory */
value = __raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
__raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);
value = __raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
__raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);
/*
* This setting is to reduce suspend/resume time.
*/
__raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);
/* Serialized CPU wakeup of Eagle */
__raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);
__raw_writel(SPREAD_USE_STANDWFI,
EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);
__raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);
exynos_pmu_config = exynos5420_pmu_config;
pm_power_off = exynos5_power_off;
pr_info("EXYNOS5420 PMU Initialized\n");
} else {
pr_info("EXYNOS: PMU not supported\n");
}
return 0;
}
