void board_init_f(ulong dummy) { dcache_disable(); socfpga_init_security_policies(); socfpga_sdram_remap_zero(); /* Assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all(); socfpga_watchdog_disable(); spl_early_init(); /* Configure the clock based on handoff */ cm_basic_init(gd->fdt_blob); #ifdef CONFIG_HW_WATCHDOG /* release osc1 watchdog timer 0 from reset */ socfpga_reset_deassert_osc1wd0(); /* reconfigure and enable the watchdog */ hw_watchdog_init(); WATCHDOG_RESET(); #endif /* CONFIG_HW_WATCHDOG */ config_dedicated_pins(gd->fdt_blob); WATCHDOG_RESET(); }
void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); unsigned long sdram_size; unsigned long reg; int ret; /* * First C code to run. Clear fake OCRAM ECC first as SBE * and DBE might triggered during power on */ reg = readl(&sysmgr_regs->eccgrp_ocram); if (reg & SYSMGR_ECC_OCRAM_SERR) writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, &sysmgr_regs->eccgrp_ocram); if (reg & SYSMGR_ECC_OCRAM_DERR) writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, &sysmgr_regs->eccgrp_ocram); memset(__bss_start, 0, __bss_end - __bss_start); socfpga_sdram_remap_zero(); debug("Freezing all I/O banks\n"); /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); if (!socfpga_is_booting_from_fpga()) { /* Put FPGA bridges into reset too. */ socfpga_bridges_reset(1); } socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); timer_init(); debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ if (cm_basic_init(cm_default_cfg)) hang(); /* Enable bootrom to configure IOs. */ sysmgr_config_warmrstcfgio(1); /* configure the IOCSR / IO buffer settings */ if (scan_mgr_configure_iocsr()) hang(); sysmgr_config_warmrstcfgio(0); /* configure the pin muxing through system manager */ sysmgr_config_warmrstcfgio(1); sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); /* De-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); socfpga_bridges_reset(0); debug("Unfreezing/Thaw all I/O banks\n"); /* unfreeze / thaw all IO banks */ sys_mgr_frzctrl_thaw_req(); #ifdef CONFIG_DEBUG_UART socfpga_per_reset(SOCFPGA_RESET(UART0), 0); debug_uart_init(); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } /* enable console uart printing */ preloader_console_init(); if (sdram_mmr_init_full(0xffffffff) != 0) { puts("SDRAM init failed.\n"); hang(); } debug("SDRAM: Calibrating PHY\n"); /* SDRAM calibration */ if (sdram_calibration_full() == 0) { puts("SDRAM calibration failed.\n"); hang(); } sdram_size = sdram_calculate_size(); debug("SDRAM: %ld MiB\n", sdram_size >> 20); /* Sanity check ensure correct SDRAM size specified */ if (get_ram_size(0, sdram_size) != sdram_size) { puts("SDRAM size check failed!\n"); hang(); } if (!socfpga_is_booting_from_fpga()) socfpga_bridges_reset(1); }