static int __init bcmring_clocksource_init(void)
{
sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
return 0;
}
static int __init bcmring_clocksource_init(void)
{
/* setup timer1 as free-running clocksource */
sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
/* setup timer3 as free-running clocksource */
sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
return 0;
}
static void __init versatile_timer_init(void)
{
u32 val;
/*
* set clock frequency:
* VERSATILE_REFCLK is 32KHz
* VERSATILE_TIMCLK is 1MHz
*/
val = readl(__io_address(VERSATILE_SCTL_BASE));
writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
__io_address(VERSATILE_SCTL_BASE));
/*
* Initialise to a known state (all timers off)
*/
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
sp804_clocksource_init(TIMER3_VA_BASE);
sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
}
/*
* Set up the clock source and clock events devices
*/
void __init realview_timer_init(unsigned int timer_irq)
{
u32 val;
/*
* set clock frequency:
* REALVIEW_REFCLK is 32KHz
* REALVIEW_TIMCLK is 1MHz
*/
val = readl(__io_address(REALVIEW_SCTL_BASE));
writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
__io_address(REALVIEW_SCTL_BASE));
/*
* Initialise to a known state (all timers off)
*/
writel(0, timer0_va_base + TIMER_CTRL);
writel(0, timer1_va_base + TIMER_CTRL);
writel(0, timer2_va_base + TIMER_CTRL);
writel(0, timer3_va_base + TIMER_CTRL);
sp804_clocksource_init(timer3_va_base, "timer3");
sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
}
int __init arch_clocksource_init(void)
{
int rc;
u32 val;
virtual_addr_t sctl_base;
/* Map control registers */
sctl_base = vmm_host_iomap(V2M_SYSCTL, 0x1000);
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
val = vmm_readl((void *)sctl_base) | SCCTRL_TIMEREN1SEL_TIMCLK;
vmm_writel(val, (void *)sctl_base);
/* Unmap control register */
rc = vmm_host_iounmap(sctl_base, 0x1000);
if (rc) {
return rc;
}
/* Map timer1 registers */
ca9x4_timer1_base = vmm_host_iomap(V2M_TIMER1, 0x1000);
/* Initialize timer1 as clocksource */
rc = sp804_clocksource_init(ca9x4_timer1_base,
"sp804_timer1", 300, 1000000, 20);
if (rc) {
return rc;
}
return VMM_OK;
}
static void __init cp_of_timer_init(void)
{
struct device_node *node;
const char *path;
void __iomem *base;
int err;
int irq;
err = of_property_read_string(of_aliases,
"arm,timer-primary", &path);
if (WARN_ON(err))
return;
node = of_find_node_by_path(path);
base = of_iomap(node, 0);
if (WARN_ON(!base))
return;
writel(0, base + TIMER_CTRL);
sp804_clocksource_init(base, node->name);
err = of_property_read_string(of_aliases,
"arm,timer-secondary", &path);
if (WARN_ON(err))
return;
node = of_find_node_by_path(path);
base = of_iomap(node, 0);
if (WARN_ON(!base))
return;
irq = irq_of_parse_and_map(node, 0);
writel(0, base + TIMER_CTRL);
sp804_clockevents_init(base, irq, node->name);
}
void __init realview_timer_init(unsigned int timer_irq)
{
u32 val;
/*
*/
val = readl(__io_address(REALVIEW_SCTL_BASE));
writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
__io_address(REALVIEW_SCTL_BASE));
/*
*/
writel(0, timer0_va_base + TIMER_CTRL);
writel(0, timer1_va_base + TIMER_CTRL);
writel(0, timer2_va_base + TIMER_CTRL);
writel(0, timer3_va_base + TIMER_CTRL);
sp804_clocksource_init(timer3_va_base, "timer3");
sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
}
static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
{
if (WARN_ON(!base || irq == NO_IRQ))
return;
sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
}
static void __init ct_ca9x4_timer_init(void)
{
writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
}
static void v2m_timer_init(void)
{
writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
sp804_clocksource_init(MMIO_P2V(V2M_TIMER1));
sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0);
}
static void __init intcp_timer_init(void)
{
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
void __init versatile_timer_init(void)
{
/*
* Initialise to a known state (all timers off)
*/
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
void __init versatile_timer_init(void)
{
/*
* Initialise to a known state (all timers off)
*/
sp804_timer_disable(TIMER0_VA_BASE);
sp804_timer_disable(TIMER1_VA_BASE);
sp804_timer_disable(TIMER2_VA_BASE);
sp804_timer_disable(TIMER3_VA_BASE);
sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
}
static void __init v2m_timer_init(void)
{
u32 scctrl;
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
"v2m-timer0");
}
int __init arch_clocksource_init(void)
{
int rc;
u32 val;
virtual_addr_t sctl_base;
/* Map control registers */
sctl_base = vmm_host_iomap(VERSATILE_SCTL_BASE, 0x1000);
/*
* set clock frequency:
* REALVIEW_REFCLK is 32KHz
* REALVIEW_TIMCLK is 1MHz
*/
val = vmm_readl((void *)sctl_base) |
(VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel);
vmm_writel(val, (void *)sctl_base);
/* Unmap control register */
rc = vmm_host_iounmap(sctl_base, 0x1000);
if (rc) {
return rc;
}
/* Configure timer1 as free running source */
/* Map timer registers */
sp804_timer1_base = vmm_host_iomap(VERSATILE_TIMER0_1_BASE, 0x1000);
sp804_timer1_base += 0x20;
/* Initialize timer1 as clocksource */
rc = sp804_clocksource_init(sp804_timer1_base,
"sp804_timer1", 300, 1000000, 20);
if (rc) {
return rc;
}
return VMM_OK;
}
