/**
* \brief Initialize SPI as master.
*/
static void spi_master_initialize(void)
{
/* Configure an SPI peripheral. */
uint32_t spi_chip_sel, spi_clk_freq, spi_clk_pol, spi_clk_pha;
spi_enable_clock(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_disable_loopback(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, spi_get_pcs(2)); // This sets the value of PCS within the Mode Register.
spi_set_variable_peripheral_select(SPI_MASTER_BASE); // PCS needs to be set within each transfer (PCS within SPI_TDR).
spi_disable_peripheral_select_decode(SPI_MASTER_BASE); // Each CS is to be connected to a single device.
spi_set_delay_between_chip_select(SPI_MASTER_BASE, SPI_DLYBCS);
/* Set communication parameters for CS0 */
spi_chip_sel = 0;
spi_clk_freq = 100000; // SPI CLK for RTC = 100kHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_16_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED); // CS rises after SPI transfers have completed.
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS1 */
spi_chip_sel = 1;
spi_clk_freq = 2000000; // SPI CLK for RTC = 4MHz.
spi_clk_pol = 0;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS2 */
spi_chip_sel = 2;
spi_clk_freq = 44000000; // SPI CLK for MEM2 = 44MHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Enable SPI Communication */
spi_enable(SPI_MASTER_BASE);
}
/** \brief Initialize the SPI in master mode.
*
* \param p_spi Base address of the SPI instance.
*
*/
void spi_master_init(Spi *p_spi)
{
spi_enable_clock(p_spi);
spi_reset(p_spi);
spi_set_master_mode(p_spi);
spi_disable_mode_fault_detect(p_spi);
spi_disable_loopback(p_spi);
spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
spi_set_fixed_peripheral_select(p_spi);
spi_disable_peripheral_select_decode(p_spi);
spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
}
/** \brief Initialize the SPI in master mode.
*
* \param p_spi Base address of the SPI instance.
*
*/
void spi_master_init(Spi *p_spi)
{
#if SAMG55
flexcom_enable(BOARD_FLEXCOM_SPI);
flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
#else
spi_enable_clock(p_spi);
#endif
spi_reset(p_spi);
spi_set_master_mode(p_spi);
spi_disable_mode_fault_detect(p_spi);
spi_disable_loopback(p_spi);
spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
spi_set_fixed_peripheral_select(p_spi);
spi_disable_peripheral_select_decode(p_spi);
spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
}
/*
* Initialise the SPI interface as a MASTER
*
*/
void spi_master_initialize(void)
{
/* Configure an SPI peripheral. */
spi_enable_clock(SPI_MASTER_BASE);
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_disable_loopback(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS);
spi_set_fixed_peripheral_select(SPI_MASTER_BASE);
spi_disable_peripheral_select_decode(SPI_MASTER_BASE);
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_configure_cs_behavior(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_enable(SPI_MASTER_BASE);
}
void spi_master_init(Spi *p_spi, int ul_cs_pin)
{
static bool init_comms = true;
if (init_comms)
{
spi_master_init_pins();
pmc_enable_periph_clk(SPI_INTERFACE_ID);
spi_reset(p_spi);
// set master mode, peripheral select, disable fault detection
spi_set_master_mode(p_spi);
spi_disable_mode_fault_detect(p_spi);
spi_disable_loopback(p_spi);
spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
spi_set_fixed_peripheral_select(p_spi);
spi_disable_peripheral_select_decode(p_spi);
init_comms = false;
}
if (ul_cs_pin >= 0)
{
pinMode(ul_cs_pin, OUTPUT);
digitalWrite(ul_cs_pin, HIGH);
}
#if defined(USE_SAM3X_DMAC)
pmc_enable_periph_clk(ID_DMAC);
dmac_disable(DMAC);
dmac_set_priority_mode(DMAC, DMAC_GCFG_ARB_CFG_FIXED);
dmac_enable(DMAC);
#endif
}
/**
* \brief Test SPI transfer.
*
* This test tests SPI read/write.
*
* \param test Current test case.
*/
static void run_spi_trans_test(const struct test_case *test)
{
spi_status_t rc;
uint16_t spi_data;
uint8_t spi_pcs;
spi_reset(CONF_TEST_SPI);
spi_set_lastxfer(CONF_TEST_SPI);
spi_set_master_mode(CONF_TEST_SPI);
spi_disable_mode_fault_detect(CONF_TEST_SPI);
spi_set_peripheral_chip_select_value(CONF_TEST_SPI, CONF_TEST_SPI_NPCS);
spi_set_clock_polarity(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_CLK_POLARITY);
spi_set_clock_phase(CONF_TEST_SPI, CONF_TEST_SPI_NPCS, SPI_CLK_PHASE);
spi_set_bits_per_transfer(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS,
(sysclk_get_cpu_hz() / TEST_CLOCK));
spi_set_transfer_delay(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_DLYBS, SPI_DLYBCT);
spi_set_variable_peripheral_select(CONF_TEST_SPI);
spi_enable_loopback(CONF_TEST_SPI);
/* Test read/write timeout: should return SPI_ERROR_TIMEOUT. */
rc = spi_write(CONF_TEST_SPI, TEST_PATTERN, TEST_PCS, 1);
test_assert_true(test, rc == SPI_ERROR_TIMEOUT,
"Test SPI Write timeout: return code should not be %d", rc);
rc = spi_read(CONF_TEST_SPI, &spi_data, &spi_pcs);
test_assert_true(test, rc == SPI_ERROR_TIMEOUT,
"Test SPI Read timeout: return code should not be %d", rc);
spi_enable(CONF_TEST_SPI);
spi_enable_interrupt(CONF_TEST_SPI, SPI_IER_TDRE|SPI_IER_RDRF);
NVIC_EnableIRQ((IRQn_Type)CONF_TEST_SPI_ID);
/* Test write: should return OK. */
rc = spi_write(CONF_TEST_SPI, TEST_PATTERN, TEST_PCS, 1);
test_assert_true(test, rc == SPI_OK,
"Test SPI Write: return code should not be %d", rc);
/* Test read: should return OK with what is sent. */
rc = spi_read(CONF_TEST_SPI, &spi_data, &spi_pcs);
test_assert_true(test, rc == SPI_OK,
"Test SPI Read: return code should not be %d", rc);
test_assert_true(test, spi_data == TEST_PATTERN,
"Unexpected SPI data: %x, should be %x",
spi_data, TEST_PATTERN);
test_assert_true(test, spi_pcs == TEST_PCS,
"Unexpected SPI PCS: %x, should be %x",
spi_pcs, TEST_PCS);
/* Check interrupts. */
test_assert_true(test, g_b_spi_interrupt_tx_ready,
"Test SPI TX interrupt not detected");
test_assert_true(test, g_b_spi_interrupt_rx_ready,
"Test SPI RX interrupt not detected");
/* Done, disable SPI and all interrupts. */
spi_disable_loopback(CONF_TEST_SPI);
spi_disable(CONF_TEST_SPI);
spi_disable_interrupt(CONF_TEST_SPI, 0xFFFFFFFF);
NVIC_DisableIRQ((IRQn_Type)CONF_TEST_SPI_ID);
}
void board_init(void)
{
ioport_init();
//SPI interface initialization
#ifdef CONF_SPI
//MISO
ioport_set_pin_peripheral_mode(PIN_PA21, IOPORT_MODE_MUX_A);
//MOSI
ioport_set_pin_peripheral_mode(PIN_PA22, IOPORT_MODE_MUX_A);
//SCK
ioport_set_pin_peripheral_mode(PIN_PA23, IOPORT_MODE_MUX_A);
//CS0
ioport_set_pin_peripheral_mode(PIN_PA24, IOPORT_MODE_MUX_A);
//CS1
ioport_set_pin_peripheral_mode(PIN_PA13, IOPORT_MODE_MUX_C);
//CS2
ioport_set_pin_peripheral_mode(PIN_PA14, IOPORT_MODE_MUX_C);
//CS3
ioport_set_pin_peripheral_mode(PIN_PB12, IOPORT_MODE_MUX_B);
spi_enable_clock(SPI);
spi_disable(SPI);
spi_reset(SPI);
spi_set_master_mode(SPI);
spi_disable_mode_fault_detect(SPI);
spi_disable_loopback(SPI);
spi_set_variable_peripheral_select(SPI);
spi_disable_peripheral_select_decode(SPI);
//spi_set_peripheral_chip_select_value(SPI, SPI_CHSEL);
//spi_set_transfer_delay(SPI, 1, 50, 0);
//spi_set_delay_between_chip_select(SPI, 0);
for(char i = 0; i < 4; i++){
spi_set_bits_per_transfer(SPI, i, 8);
//spi_set_baudrate_div(SPI, i, spi_calc_baudrate_div(1000000, sysclk_get_cpu_hz()));
spi_set_baudrate_div(SPI, i, (sysclk_get_cpu_hz() / 500000));
spi_configure_cs_behavior(SPI, i, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI, i, 0);
spi_set_clock_phase(SPI, i, 0);
}
spi_enable(SPI);
#endif
//USART0 initialization
#ifdef CONF_USART0
//USART0 RXD
ioport_set_pin_peripheral_mode(PIN_PA11, IOPORT_MODE_MUX_A);
#if SAM4L
sysclk_enable_peripheral_clock(USART0);
#endif
//USART0 configuration struct
const sam_usart_opt_t usart0_console_settings = {
CONF_USART_0_BAUDRATE,
CONF_USART_0_CHAR_LENGTH,
CONF_USART_0_PARITY,
CONF_USART_0_STOP_BITS,
US_MR_CHMODE_NORMAL
};
usart_init_rs232(USART0, &usart0_console_settings, sysclk_get_main_hz());
usart_enable_tx(USART0);
usart_enable_rx(USART0);
usart_enable_interrupt(USART0, US_IER_RXRDY);
NVIC_SetPriority(USART0_IRQn, 10);
NVIC_EnableIRQ(USART0_IRQn);
#endif
//USART1 initialization
#ifdef CONF_USART1
//USART1 TXD
ioport_set_pin_peripheral_mode(PIN_PA16, IOPORT_MODE_MUX_A);
//USART1 RXD
ioport_set_pin_peripheral_mode(PIN_PA15, IOPORT_MODE_MUX_A);
#if SAM4L
sysclk_enable_peripheral_clock(USART1);
#endif
//USART1 configuration struct
const sam_usart_opt_t usart1_console_settings = {
CONF_USART_1_BAUDRATE,
CONF_USART_1_CHAR_LENGTH,
CONF_USART_1_PARITY,
CONF_USART_1_STOP_BITS,
US_MR_CHMODE_NORMAL
};
usart_init_rs232(USART1, &usart1_console_settings, sysclk_get_main_hz());
usart_enable_tx(USART1);
usart_enable_rx(USART1);
usart_enable_interrupt(USART1, US_IER_RXRDY);
//NVIC_SetPriority(USART0_IRQn, 10);
NVIC_EnableIRQ(USART1_IRQn);
#endif
#ifdef CONF_TWIMS1
//SDA
ioport_set_pin_peripheral_mode(PIN_PB00, IOPORT_MODE_MUX_A);
//SCL
ioport_set_pin_peripheral_mode(PIN_PB01, IOPORT_MODE_MUX_A);
/* Set TWIM options */
uint32_t cpu_speed = 0;
cpu_speed = sysclk_get_peripheral_bus_hz(EXAMPLE_TWIM);
struct twim_config opts = {
.twim_clk = sysclk_get_cpu_hz(), //Importante
.speed = TWIM_MASTER_SPEED,
.hsmode_speed = 0,
.data_setup_cycles = 0,
.hsmode_data_setup_cycles = 0,
.smbus = false,
.clock_slew_limit = 0,
.clock_drive_strength_low = 0,
.data_slew_limit = 0,
.data_drive_strength_low = 0,
.hs_clock_slew_limit = 0,
.hs_clock_drive_strength_high = 0,
.hs_clock_drive_strength_low = 0,
.hs_data_slew_limit = 0,
.hs_data_drive_strength_low = 0,
};
/* Initialize the TWIM Module */
twim_set_callback(EXAMPLE_TWIM, 0, twim_default_callback, 1);
twim_set_config(EXAMPLE_TWIM, &opts);
#endif
//ADS 1294R initialization
#ifdef CONF_ADS
ADS_ioconfig();
Soft_Reset_ADS1298();
delay_us(50);
Stop_Read_Data_Continuous();
/*Configuration register 1*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_1_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x06);
/*Configuration register 2*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_2_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Configuration register 3*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_3_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0xDC);
/*Channel 1 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_1_SET_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Channel 2 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_2_SET_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Channel 3 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_3_SET_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*RLD_SENSP register*/
ADS1298_SPI_Address_Byte_Count(WRITE_RIGHT_LEG_DRIVE_SENSE_POSITIVE_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x0F);
/*RLD_SENSN register*/
ADS1298_SPI_Address_Byte_Count(WRITE_RIGHT_LEG_DRIVE_SENSE_NEGATIVE_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x0F);
/*Respiration control register*/
//Respiration channel not enabled
#endif
}