void spi_master_close(const spi_master_hw_instance_t spi_master_hw_instance) { #if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE) volatile spi_master_instance_t * p_spi_instance = spi_master_get_instance( spi_master_hw_instance); APP_ERROR_CHECK_BOOL(p_spi_instance != NULL); /* Disable interrupt */ APP_ERROR_CHECK(sd_nvic_ClearPendingIRQ(p_spi_instance->irq_type)); APP_ERROR_CHECK(sd_nvic_DisableIRQ(p_spi_instance->irq_type)); p_spi_instance->p_nrf_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos); /* Set Slave Select pin as input with pull-up. */ nrf_gpio_pin_set(p_spi_instance->pin_slave_select); nrf_gpio_cfg_input(p_spi_instance->pin_slave_select, NRF_GPIO_PIN_PULLUP); p_spi_instance->pin_slave_select = (uint8_t)0xFF; /* Disconnect pins from SPI hardware */ p_spi_instance->p_nrf_spi->PSELSCK = (uint32_t)SPI_PIN_DISCONNECTED; p_spi_instance->p_nrf_spi->PSELMOSI = (uint32_t)SPI_PIN_DISCONNECTED; p_spi_instance->p_nrf_spi->PSELMISO = (uint32_t)SPI_PIN_DISCONNECTED; /* Reset to default values */ spi_master_init_hw_instance(NULL, (IRQn_Type)0, p_spi_instance, false); #else return; #endif }
/** * @brief Function for event handler registration. */ __INLINE void spi_master_evt_handler_reg(const spi_master_hw_instance_t spi_master_hw_instance, spi_master_event_handler_t event_handler) { #if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE) spi_master_instance_t * spi_instance = spi_master_get_instance(spi_master_hw_instance); spi_instance->callback_event_handler = event_handler; #else return; #endif }
/** * @brief Function for getting current state of the SPI master driver. */ __INLINE spi_master_state_t spi_master_get_state( const spi_master_hw_instance_t spi_master_hw_instance) { #if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE) spi_master_instance_t * spi_instance = spi_master_get_instance(spi_master_hw_instance); return spi_instance->state; #else return SPI_MASTER_STATE_DISABLED; #endif }
/** * @brief SPI0 interrupt handler. */ void SPI1_TWI1_IRQHandler(void) { if ((NRF_SPI1->EVENTS_READY == 1) && (NRF_SPI1->INTENSET & SPI_INTENSET_READY_Msk)) { NRF_SPI1->EVENTS_READY = 0; volatile spi_master_instance_t * p_spi_instance = spi_master_get_instance(SPI_MASTER_1); spi_master_send_recv_irq(p_spi_instance); } }
/** * @brief SPI0 interrupt handler. */ void SPI0_TWI0_IRQHandler(void) { if (NRF_SPI0->EVENTS_READY != 0) { NRF_SPI0->EVENTS_READY = 0; spi_master_instance_t * p_spi_instance = spi_master_get_instance(SPI_MASTER_0); spi_master_send_recv_irq(p_spi_instance); } }
__INLINE void spi_master_evt_handler_reg(const spi_master_hw_instance_t spi_master_hw_instance, spi_master_event_handler_t event_handler) { #if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE) volatile spi_master_instance_t * p_spi_instance = spi_master_get_instance( spi_master_hw_instance); APP_ERROR_CHECK_BOOL(p_spi_instance != NULL); p_spi_instance->callback_event_handler = event_handler; #else return; #endif }
__INLINE spi_master_state_t spi_master_get_state( const spi_master_hw_instance_t spi_master_hw_instance) { #if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE) volatile spi_master_instance_t * p_spi_instance = spi_master_get_instance( spi_master_hw_instance); APP_ERROR_CHECK_BOOL(p_spi_instance != NULL); return p_spi_instance->state; #else return SPI_MASTER_STATE_DISABLED; #endif }
/** * @brief Function for transmitting data between SPI master and SPI slave. */ uint32_t spi_master_send_recv(const spi_master_hw_instance_t spi_master_hw_instance, uint8_t * const p_tx_buf, const uint16_t tx_buf_len, uint8_t * const p_rx_buf, const uint16_t rx_buf_len) { #if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE) spi_master_instance_t * p_spi_instance = spi_master_get_instance(spi_master_hw_instance); uint32_t err_code = NRF_SUCCESS; uint16_t max_length = 0; if (p_spi_instance->state == SPI_MASTER_STATE_IDLE) { NVIC_DisableIRQ(p_spi_instance->irq_type); max_length = (rx_buf_len > tx_buf_len) ? rx_buf_len : tx_buf_len; if (max_length > 0) { p_spi_instance->state = SPI_MASTER_STATE_BUSY; p_spi_instance->start_flag = true; //abort_flag should set by abort and cleared only by restart p_spi_instance->bytes_count = 0; p_spi_instance->max_length = max_length; spi_master_buffer_release(&(p_spi_instance->p_tx_buffer), &(p_spi_instance->tx_length)); spi_master_buffer_release(&(p_spi_instance->p_rx_buffer), &(p_spi_instance->rx_length)); /* Initialize buffers */ spi_master_buffer_init(p_tx_buf, tx_buf_len, &(p_spi_instance->p_tx_buffer), &(p_spi_instance->tx_length), &(p_spi_instance->tx_index)); spi_master_buffer_init(p_rx_buf, rx_buf_len, &(p_spi_instance->p_rx_buffer), &(p_spi_instance->rx_length), &(p_spi_instance->rx_index)); nrf_gpio_pin_clear(p_spi_instance->pin_slave_select); spi_master_send_initial_bytes(p_spi_instance); spi_master_signal_evt(p_spi_instance, SPI_MASTER_EVT_TRANSFER_STARTED, max_length); } else { err_code = NRF_ERROR_INVALID_PARAM; } NVIC_EnableIRQ(p_spi_instance->irq_type); } else { err_code = NRF_ERROR_BUSY; } return err_code; #else return NRF_ERROR_NOT_SUPPORTED; #endif }
/** * @brief Function for aborting transfer */ uint32_t spi_master_abort(const spi_master_hw_instance_t spi_master_hw_instance) { spi_master_instance_t * p_spi_instance = spi_master_get_instance(spi_master_hw_instance); NVIC_DisableIRQ(p_spi_instance->irq_type); if (p_spi_instance->state == SPI_MASTER_STATE_BUSY) { //set_flag - but only when there are events pending //ignore when in IDLE - must be able to restart a completed transfer p_spi_instance->abort_flag = true; } NVIC_EnableIRQ(p_spi_instance->irq_type); return NRF_SUCCESS; }
/** * @brief Function for restarting transfer */ uint32_t spi_master_restart(const spi_master_hw_instance_t spi_master_hw_instance) { spi_master_instance_t * p_spi_instance = spi_master_get_instance(spi_master_hw_instance); NVIC_DisableIRQ(p_spi_instance->irq_type); spi_master_signal_evt(p_spi_instance, SPI_MASTER_EVT_TRANSFER_RESTARTED, 0); p_spi_instance->state = SPI_MASTER_STATE_BUSY; p_spi_instance->bytes_count = 0; p_spi_instance->tx_index = 0; p_spi_instance->rx_index = 0; p_spi_instance->start_flag = true; p_spi_instance->abort_flag = false; //you should force clearing abort flag - no other way for 1 byte transfer nrf_gpio_pin_clear(p_spi_instance->pin_slave_select); spi_master_send_initial_bytes(p_spi_instance); NVIC_EnableIRQ(p_spi_instance->irq_type); return NRF_SUCCESS; }
uint32_t spi_master_send_recv(const spi_master_hw_instance_t spi_master_hw_instance, uint8_t * const p_tx_buf, const uint16_t tx_buf_len, uint8_t * const p_rx_buf, const uint16_t rx_buf_len) { #if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE) volatile spi_master_instance_t * p_spi_instance = spi_master_get_instance( spi_master_hw_instance); APP_ERROR_CHECK_BOOL(p_spi_instance != NULL); uint32_t err_code = NRF_SUCCESS; uint16_t max_length = 0; uint8_t nested_critical_region = 0; //Check if disable all IRQs flag is set if (p_spi_instance->disable_all_irq) { //Disable interrupts. APP_ERROR_CHECK(sd_nvic_critical_region_enter(&nested_critical_region)); } else { //Disable interrupt SPI. APP_ERROR_CHECK(sd_nvic_DisableIRQ(p_spi_instance->irq_type)); } //Initialize and perform data transfer if (p_spi_instance->state == SPI_MASTER_STATE_IDLE) { max_length = (rx_buf_len > tx_buf_len) ? rx_buf_len : tx_buf_len; if (max_length > 0) { p_spi_instance->state = SPI_MASTER_STATE_BUSY; p_spi_instance->bytes_count = 0; p_spi_instance->started_flag = false; p_spi_instance->max_length = max_length; /* Initialize buffers */ spi_master_buffer_init(p_tx_buf, tx_buf_len, &(p_spi_instance->p_tx_buffer), &(p_spi_instance->tx_length), &(p_spi_instance->tx_index)); spi_master_buffer_init(p_rx_buf, rx_buf_len, &(p_spi_instance->p_rx_buffer), &(p_spi_instance->rx_length), &(p_spi_instance->rx_index)); nrf_gpio_pin_clear(p_spi_instance->pin_slave_select); spi_master_send_initial_bytes(p_spi_instance); } else { err_code = NRF_ERROR_INVALID_PARAM; } } else { err_code = NRF_ERROR_BUSY; } //Check if disable all IRQs flag is set. if (p_spi_instance->disable_all_irq) { //Enable interrupts. APP_ERROR_CHECK(sd_nvic_critical_region_exit(nested_critical_region)); } else { //Enable SPI interrupt. APP_ERROR_CHECK(sd_nvic_EnableIRQ(p_spi_instance->irq_type)); } return err_code; #else return NRF_ERROR_NOT_SUPPORTED; #endif }
uint32_t spi_master_open(const spi_master_hw_instance_t spi_master_hw_instance, spi_master_config_t const * const p_spi_master_config) { #if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE) /* Check against null */ if (p_spi_master_config == NULL) { return NRF_ERROR_NULL; } volatile spi_master_instance_t * p_spi_instance = spi_master_get_instance( spi_master_hw_instance); APP_ERROR_CHECK_BOOL(p_spi_instance != NULL); switch (spi_master_hw_instance) { #ifdef SPI_MASTER_0_ENABLE case SPI_MASTER_0: spi_master_init_hw_instance(NRF_SPI0, SPI0_TWI0_IRQn, p_spi_instance, p_spi_master_config->SPI_DisableAllIRQ); break; #endif /* SPI_MASTER_0_ENABLE */ #ifdef SPI_MASTER_1_ENABLE case SPI_MASTER_1: spi_master_init_hw_instance(NRF_SPI1, SPI1_TWI1_IRQn, p_spi_instance, p_spi_master_config->SPI_DisableAllIRQ); break; #endif /* SPI_MASTER_1_ENABLE */ default: break; } //A Slave select must be set as high before setting it as output, //because during connect it to the pin it causes glitches. nrf_gpio_pin_set(p_spi_master_config->SPI_Pin_SS); nrf_gpio_cfg_output(p_spi_master_config->SPI_Pin_SS); nrf_gpio_pin_set(p_spi_master_config->SPI_Pin_SS); //Configure GPIO nrf_gpio_cfg_output(p_spi_master_config->SPI_Pin_SCK); nrf_gpio_cfg_output(p_spi_master_config->SPI_Pin_MOSI); nrf_gpio_cfg_input(p_spi_master_config->SPI_Pin_MISO, NRF_GPIO_PIN_NOPULL); p_spi_instance->pin_slave_select = p_spi_master_config->SPI_Pin_SS; /* Configure SPI hardware */ p_spi_instance->p_nrf_spi->PSELSCK = p_spi_master_config->SPI_Pin_SCK; p_spi_instance->p_nrf_spi->PSELMOSI = p_spi_master_config->SPI_Pin_MOSI; p_spi_instance->p_nrf_spi->PSELMISO = p_spi_master_config->SPI_Pin_MISO; p_spi_instance->p_nrf_spi->FREQUENCY = p_spi_master_config->SPI_Freq; p_spi_instance->p_nrf_spi->CONFIG = (uint32_t)(p_spi_master_config->SPI_CONFIG_CPHA << SPI_CONFIG_CPHA_Pos) | (p_spi_master_config->SPI_CONFIG_CPOL << SPI_CONFIG_CPOL_Pos) | (p_spi_master_config->SPI_CONFIG_ORDER << SPI_CONFIG_ORDER_Pos); /* Clear waiting interrupts and events */ p_spi_instance->p_nrf_spi->EVENTS_READY = 0; APP_ERROR_CHECK(sd_nvic_ClearPendingIRQ(p_spi_instance->irq_type)); APP_ERROR_CHECK(sd_nvic_SetPriority(p_spi_instance->irq_type, p_spi_master_config->SPI_PriorityIRQ)); /* Clear event handler */ p_spi_instance->callback_event_handler = NULL; /* Enable interrupt */ p_spi_instance->p_nrf_spi->INTENSET = (SPI_INTENSET_READY_Set << SPI_INTENCLR_READY_Pos); APP_ERROR_CHECK(sd_nvic_EnableIRQ(p_spi_instance->irq_type)); /* Enable SPI hardware */ p_spi_instance->p_nrf_spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos); /* Change state to IDLE */ p_spi_instance->state = SPI_MASTER_STATE_IDLE; return NRF_SUCCESS; #else return NRF_ERROR_NOT_SUPPORTED; #endif }