int main (void)
{
//! [config_instance]
struct spi_master_vec_config spi_config;
//! [config_instance]
//! [init_system]
system_init();
//! [init_system]
//! [set_up_config_instance]
spi_master_vec_get_config_defaults(&spi_config);
spi_config.baudrate = 200000;
spi_config.transfer_mode = SPI_TRANSFER_MODE_3;
spi_config.mux_setting = EXT1_SPI_SERCOM_MUX_SETTING;
spi_config.pinmux_pad0 = EXT1_SPI_SERCOM_PINMUX_PAD0;
spi_config.pinmux_pad1 = EXT1_SPI_SERCOM_PINMUX_PAD1;
spi_config.pinmux_pad2 = EXT1_SPI_SERCOM_PINMUX_PAD2;
spi_config.pinmux_pad3 = EXT1_SPI_SERCOM_PINMUX_PAD3;
//! [set_up_config_instance]
//! [init_instance]
spi_master_vec_init(&spi_master, EXT1_SPI_MODULE, &spi_config);
//! [init_instance]
//! [enable_instance]
spi_master_vec_enable(&spi_master);
//! [enable_instance]
//! [start_reception_wait]
spi_master_vec_transceive_buffer_wait(&spi_master, NULL, rx_buffers);
//! [start_reception_wait]
//! [start_transmission]
spi_master_vec_transceive_buffer_job(&spi_master, tx_buffers, NULL);
//! [start_transmission]
//! [start_transception]
while (spi_master_vec_transceive_buffer_job(&spi_master, tx_buffers, rx_buffers) == STATUS_BUSY) {
/* Try to start transfer until it succeeds. */
}
//! [start_transception]
//! [wait_transception]
spi_master_vec_get_job_status_wait(&spi_master);
//! [wait_transception]
while (1) {
}
}
static void test_at25dfx_init(void)
{
struct at25dfx_chip_config at25dfx_chip_config;
#ifdef CONF_TEST_VECTORED_MASTER
struct spi_master_vec_config at25dfx_spi_config;
at25dfx_spi_master_vec_get_config_defaults(&at25dfx_spi_config);
at25dfx_spi_config.baudrate = AT25DFX_CLOCK_SPEED;
#else
struct spi_config at25dfx_spi_config;
at25dfx_spi_get_config_defaults(&at25dfx_spi_config);
at25dfx_spi_config.mode_specific.master.baudrate = AT25DFX_CLOCK_SPEED;
#endif
at25dfx_spi_config.mux_setting = AT25DFX_SPI_PINMUX_SETTING;
at25dfx_spi_config.pinmux_pad0 = AT25DFX_SPI_PINMUX_PAD0;
at25dfx_spi_config.pinmux_pad1 = AT25DFX_SPI_PINMUX_PAD1;
at25dfx_spi_config.pinmux_pad2 = AT25DFX_SPI_PINMUX_PAD2;
at25dfx_spi_config.pinmux_pad3 = AT25DFX_SPI_PINMUX_PAD3;
#ifdef CONF_TEST_VECTORED_MASTER
spi_master_vec_init(&at25dfx_spi, AT25DFX_SPI, &at25dfx_spi_config);
spi_master_vec_enable(&at25dfx_spi);
#else
spi_init(&at25dfx_spi, AT25DFX_SPI, &at25dfx_spi_config);
spi_enable(&at25dfx_spi);
#endif
// Initialize real and dummy chip
at25dfx_chip_config.type = AT25DFX_MEM_TYPE;
at25dfx_chip_config.cs_pin = AT25DFX_CS;
at25dfx_chip_init(&at25dfx_chip, &at25dfx_spi, &at25dfx_chip_config);
at25dfx_chip_config.cs_pin = EXT1_PIN_SPI_SS_1;
at25dfx_chip_init(&at25dfx_dummy, &at25dfx_spi, &at25dfx_chip_config);
}
OSStatus host_platform_bus_init( void )
{
#ifndef USE_OWN_SPI_DRV
struct spi_master_vec_config spi;
#else
pdc_packet_t pdc_spi_packet;
#endif
OSStatus result;
MCU_CLOCKS_NEEDED();
spi_disable_interrupt(SPI_MASTER_BASE, 0xffffffff);
//Disable_global_interrupt();//TBD!
result = mico_rtos_init_semaphore( &spi_transfer_finished_semaphore, 1 );
if ( result != kNoErr )
{
return result;
}
mico_gpio_initialize( (mico_gpio_t)MICO_GPIO_9, INPUT_PULL_UP );
//ioport_port_mask_t ul_mask = ioport_pin_to_mask(CREATE_IOPORT_PIN(PORTA,24));
//pio_set_input(PIOA,ul_mask, PIO_PULLUP|PIO_DEBOUNCE);
mico_gpio_enable_IRQ( (mico_gpio_t)MICO_GPIO_9, IRQ_TRIGGER_RISING_EDGE, spi_irq_handler, NULL );
#ifndef HARD_CS_NSS0
mico_gpio_initialize( MICO_GPIO_15, OUTPUT_PUSH_PULL);//spi ss/cs
mico_gpio_output_high( MICO_GPIO_15 );//MICO_GPIO_15 TBD!
#else
ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);//TBD!
#endif
/* set PORTB 01 to high to put WLAN module into g_SPI mode */
mico_gpio_initialize( (mico_gpio_t)WL_GPIO0, OUTPUT_PUSH_PULL );
mico_gpio_output_high( (mico_gpio_t)WL_GPIO0 );
#ifdef USE_OWN_SPI_DRV
#if (SAMG55)
/* Enable the peripheral and set SPI mode. */
flexcom_enable(BOARD_FLEXCOM_SPI);
flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
#else
/* Configure an SPI peripheral. */
pmc_enable_periph_clk(SPI_ID);
#endif
//Init pdc, and clear RX TX.
spi_m_pdc = spi_get_pdc_base(SPI_MASTER_BASE);
pdc_spi_packet.ul_addr = NULL;
pdc_spi_packet.ul_size = 3;
pdc_tx_init(spi_m_pdc, &pdc_spi_packet, NULL);
pdc_rx_init(spi_m_pdc, &pdc_spi_packet, NULL);
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_lastxfer(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
#ifdef HARD_CS_NSS0
//spi_enable_peripheral_select_decode(SPI_MASTER_BASE);
//spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS); //use soft nss comment here
#endif
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / SPI_BAUD_RATE));
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */
/* otherwise FreeRTOS will not be able to mask the interrupt */
/* keep in mind that ARMCM3 interrupt priority logic is inverted, the highest value */
/* is the lowest priority */
/* Configure SPI interrupts . */
spi_enable_interrupt(SPI_MASTER_BASE, SPI_IER_RXBUFF);
//spi_enable_interrupt(SPI_MASTER_BASE, SPI_IER_NSSR | SPI_IER_RXBUFF);
NVIC_DisableIRQ(SPI_IRQn);
//irq_register_handler(SPI_IRQn, 3);
NVIC_ClearPendingIRQ(SPI_IRQn);
NVIC_SetPriority(SPI_IRQn, 3);
NVIC_EnableIRQ(SPI_IRQn);
spi_enable(SPI_MASTER_BASE);
#else
spi.baudrate = SPI_BAUD_RATE;
if (STATUS_OK != spi_master_vec_init(&spi_master, SPI_MASTER_BASE, &spi)) {
return -1;
}
spi_master_vec_enable(&spi_master);
#endif
//if (!Is_global_interrupt_enabled())
// Enable_global_interrupt();
MCU_CLOCKS_NOT_NEEDED();
return kNoErr;
}
