void spi_setup(void) {
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN);
/* For spi signal pins */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPAEN);
/* For spi mode select on the l3gd20 */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPEEN);
/* Setup GPIOE3 pin for spi mode l3gd20 select. */
gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3);
/* Start with spi communication disabled */
gpio_set(GPIOE, GPIO3);
/* Setup GPIO pins for AF5 for SPI1 signals. */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7);
gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO6 | GPIO7);
//spi initialization;
spi_set_master_mode(SPI1);
spi_set_baudrate_prescaler(SPI1, SPI_CR1_BR_FPCLK_DIV_64);
spi_set_clock_polarity_0(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_full_duplex_mode(SPI1);
spi_set_unidirectional_mode(SPI1); /* bidirectional but in 3-wire */
spi_set_data_size(SPI1, SPI_CR2_DS_8BIT);
spi_enable_software_slave_management(SPI1);
spi_send_msb_first(SPI1);
spi_set_nss_high(SPI1);
//spi_enable_ss_output(SPI1);
spi_fifo_reception_threshold_8bit(SPI1);
SPI_I2SCFGR(SPI1) &= ~SPI_I2SCFGR_I2SMOD;
spi_enable(SPI1);
}
/* Setup the SPI bus. This function may cause spurious signals on the SPI bus,
* so it should be called before the transaction starts (i.e. while SS is high).
* -CPOL is the clock polarity (0 or 1)
* -CPHA is the clock phase (0 or 1)
* -baudrate is one of libopencm3's SPI_CR1_BAUDRATE_FPCLK_DIV_X values.
* Baudrates are derived from the low-speed peripheral clock APB1.
* -firstbit is either SPI_CR1_MSBFIRST or SPI_CR1_LSBFIRST. */
void setup_spi(uint8_t cpol, uint8_t cpha, uint8_t baudrate, uint8_t firstbit){
disable_and_reset_spi_properly();
SPI_CR1(SPI3) &= 0xFFC7; /* Mask off baudrate bits. */
SPI_CR1(SPI3) |= baudrate;
if(0 == cpol){
spi_set_clock_polarity_0(SPI3);
} else {
spi_set_clock_polarity_1(SPI3);
}
if(0 == cpha){
spi_set_clock_phase_0(SPI3);
} else {
spi_set_clock_polarity_1(SPI3);
}
spi_set_unidirectional_mode(SPI3); /* bidirectional but in 3-wire */
spi_set_full_duplex_mode(SPI3);
SPI_CR1(SPI3) &= ~SPI_CR1_LSBFIRST;
SPI_CR1(SPI3) |= firstbit;
spi_enable_software_slave_management(SPI3);
spi_set_nss_high(SPI3);
spi_set_master_mode(SPI3);
spi_set_data_size(SPI3, SPI_CR2_DS_8BIT);
spi_fifo_reception_threshold_8bit(SPI3);
SPI_I2SCFGR(SPI3) &= ~SPI_I2SCFGR_I2SMOD;
/* All DMA configuration is handled by tx_spi(), rx_spi(), and rxtx_spi(). */
}
void init_codec() {
/* enable clock for Aux power and power up the regulators */
rcc_peripheral_enable_clock(&CODEC_PWR_APB, CODEC_RCC_PWR);
gpio_set_mode(CODEC_PWR_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_PWR);
gpio_set(CODEC_PWR_PORT, CODEC_PWR);
/* enable SPI1 clock */
rcc_peripheral_enable_clock(&CODEC_SPI_APB, CODEC_RCC_SPI);
/* enable clock for the chip select pin */
rcc_peripheral_enable_clock(&CODEC_IOS_APB, CODEC_RCC_IOS);
/* enable clock for the RST/DREQ lines */
rcc_peripheral_enable_clock(&CODEC_IOI_APB, CODEC_RCC_IOI);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
/* set the pin modes for the SPI pins */
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_CS);
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, CODEC_MOSI);
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, CODEC_SCK);
gpio_set_mode(CODEC_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, CODEC_MISO);
/* set the modes for the reset and busy pins */
gpio_set_mode(CODEC_RST_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_RST);
gpio_set_mode(CODEC_DREQ_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, CODEC_DREQ);
gpio_clear(CODEC_RST_PORT, CODEC_RST);
/* configure the SPI port */
spi_set_unidirectional_mode(CODEC_SPI);
spi_disable_crc(CODEC_SPI);
spi_set_dff_8bit(CODEC_SPI);
spi_set_full_duplex_mode(CODEC_SPI);
spi_enable_software_slave_management(CODEC_SPI);
spi_set_nss_high(CODEC_SPI);
spi_set_baudrate_prescaler(CODEC_SPI, SPI_CR1_BR_FPCLK_DIV_32);
spi_set_master_mode(CODEC_SPI);
spi_send_msb_first(CODEC_SPI);
spi_set_clock_polarity_0(CODEC_SPI);
spi_set_clock_phase_0(CODEC_SPI);
spi_disable_ss_output(CODEC_SPI);
spi_enable(CODEC_SPI);
/* disable chip select */
gpio_set(CODEC_PORT, CODEC_CS);
/* make sure reset is not asserted */
gpio_set(CODEC_RST_PORT, CODEC_RST);
return;
}
/* *************** HAL API functions **************************************** */
void hal_init( void ) {
int ret = 0;
/* Reset variables used in file. */
hal_system_time = 0;
// hal_reset_flags();
/* Enable GPIOA clock. Enable AFIO clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR,
RCC_APB2ENR_IOPAEN |
RCC_APB2ENR_IOPBEN |
RCC_APB2ENR_IOPCEN |
RCC_APB2ENR_SPI1EN |
RCC_APB2ENR_AFIOEN );
/* The following pins are output pins. */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,RST); //reset
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SLP_TR); //sleep
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SEL); //cs
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
SCK | MOSI | MISO); //sck mosi miso
spi_disable(RF_SPI);
SPI2_I2SCFGR = 0;
/* Setup SPI parameters. */
spi_init_master(RF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_16, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
spi_set_unidirectional_mode(RF_SPI);
spi_set_full_duplex_mode(RF_SPI); /* Not receive-only */
spi_enable_software_slave_management(RF_SPI);
spi_set_nss_high(RF_SPI);
spi_enable_ss_output(RF_SPI); /* Required, see NSS, 25.3.1 section. */
/* Finally enable the SPI. */
spi_enable(RF_SPI);
/* Set GPIO4 (in GPIO port C) to 'input float'. */
gpio_set_mode(RF_IRQ_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, RF_IRQ_PIN);
gpio_clear(RF_IRQ_PORT, RF_IRQ_PIN);
/* Configure the EXTI subsystem. */
exti_select_source(EXTI4, RF_IRQ_PORT);
exti_set_trigger(EXTI4, EXTI_TRIGGER_RISING);
exti_enable_request(EXTI4);
exti_reset_request(EXTI4);
PRINTF("Enabling interrupts\r\n");
/* Enable EXTI0 interrupt. */
nvic_enable_irq(NVIC_EXTI4_IRQ);
nvic_set_priority(NVIC_EXTI4_IRQ,4);
//@@@!? timer_init();
// ret = trx_init();
// if(ret!=0)
// {
// PRINTF("rf231:hal init failed\r\n");
// }else
// {
// PRINTF("rf231:hal init success\r\n");
// }
}
void spi_start(void)
{
/* Reset flash chip */
gpio_clear(GPIOD, BL_SPI2_RST);
wait(10);
gpio_set(GPIOD, BL_SPI2_RST);
wait(10);
gpio_set(GPIOD, BL_SPI2_WP);
/* No WriteProtect, Set Chip select to 1(no select) */
gpio_set(GPIOB, BL_SPI2_NSS);
/* Reset and disable SPI */
spi_reset(SPI2);
/* Disable I2S */
SPI2_I2SCFGR = 0;
/* CR1 */
spi_set_clock_phase_0(SPI2); /* CPHA = 0 */
spi_set_clock_polarity_0(SPI2); /* CPOL = 0 */
spi_send_msb_first(SPI2); /* LSB = 0 */
spi_set_full_duplex_mode(SPI2); /* RXONLY = 0 */
spi_set_unidirectional_mode(SPI2); /* BIDI = 0 */
spi_enable_software_slave_management(SPI2); /* SSM = 1 */
spi_set_nss_high(SPI2); /* SSI = 1 */
spi_set_master_mode(SPI2); /* MSTR = 1 */
spi_set_dff_8bit(SPI2); /* DFf = 8 bit */
// spi_enable_crc(SPI2);
/* XXX: Too fast? Maybe DIV_4 will be better? */
spi_set_baudrate_prescaler(SPI2, SPI_CR1_BR_FPCLK_DIV_2);
/* CR2 */
spi_enable_ss_output(SPI2); /* SSOE = 1 */
/* Disable regular interrupt flags */
spi_disable_tx_buffer_empty_interrupt(SPI2);
spi_disable_rx_buffer_not_empty_interrupt(SPI2);
spi_disable_error_interrupt(SPI2);
/* Enabling RX/TX DMA flags */
spi_enable_tx_dma(SPI2);
spi_enable_rx_dma(SPI2);
d_print("REG: %lu:%lu\r\n", SPI_CR1(SPI2), SPI_CR2(SPI2));
spi_enable(SPI2);
}
static void spi_setup(void)
{
/* The DOGM128 display is connected to SPI2, so initialise it. */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN);
spi_set_unidirectional_mode(DOGM128_SPI); /* We want to send only. */
spi_disable_crc(DOGM128_SPI); /* No CRC for this slave. */
spi_set_dff_8bit(DOGM128_SPI); /* 8-bit dataword-length */
spi_set_full_duplex_mode(DOGM128_SPI); /* Not receive-only */
/* We want to handle the CS signal in software. */
spi_enable_software_slave_management(DOGM128_SPI);
spi_set_nss_high(DOGM128_SPI);
/* PCLOCK/256 as clock. */
spi_set_baudrate_prescaler(DOGM128_SPI, SPI_CR1_BR_FPCLK_DIV_256);
/* We want to control everything and generate the clock -> master. */
spi_set_master_mode(DOGM128_SPI);
spi_set_clock_polarity_1(DOGM128_SPI); /* SCK idle state high. */
/* Bit is taken on the second (rising edge) of SCK. */
spi_set_clock_phase_1(DOGM128_SPI);
spi_enable_ss_output(DOGM128_SPI);
spi_enable(DOGM128_SPI);
}
int devspi_create(const struct spi_config *conf)
{
struct dev_spi *spi = NULL;
if (!conf)
return -EINVAL;
if (conf->base == 0)
return -EINVAL;
if ((conf->idx < 0) || (conf->idx > MAX_SPIS))
return -EINVAL;
spi = kalloc(sizeof(struct dev_spi));
if (!spi)
return -ENOMEM;
/* Claim pins for SCK/MOSI/MISO */
gpio_create(&mod_spi, &conf->pio_sck);
gpio_create(&mod_spi, &conf->pio_mosi);
gpio_create(&mod_spi, &conf->pio_miso);
/* Erase spi content */
memset(spi, 0, sizeof(struct dev_spi));
/* Enable clocks */
rcc_periph_clock_enable(conf->rcc);
rcc_periph_clock_enable(conf->dma_rcc);
/* Startup routine */
//spi_disable(conf->base);
/**********************************/
/* reset SPI1 */
spi_reset(conf->base);
/* init SPI1 master */
spi_init_master(conf->base,
SPI_CR1_BAUDRATE_FPCLK_DIV_64,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
/* enable SPI1 first */
spi_enable(conf->base);
/**********************************/
#if 0
spi_set_master_mode(conf->base);
spi_set_baudrate_prescaler(conf->base, SPI_CR1_BR_FPCLK_DIV_256); /* TODO: Calculate prescaler from baudrate */
if(conf->polarity == 0)
spi_set_clock_polarity_0(conf->base);
else
spi_set_clock_polarity_1(conf->base);
if(conf->phase == 0) spi_set_clock_phase_0(conf->base);
else
spi_set_clock_phase_1(conf->base);
if(conf->rx_only == 0)
spi_set_full_duplex_mode(conf->base);
else
spi_set_receive_only_mode(conf->base);
if(conf->bidir_mode == 0)
spi_set_unidirectional_mode(conf->base);
else
spi_set_bidirectional_mode(conf->base);
if(conf->dff_16)
spi_set_dff_16bit(conf->base);
else
spi_set_dff_8bit(conf->base);
if(conf->enable_software_slave_management)
spi_enable_software_slave_management(conf->base);
else
spi_disable_software_slave_management(conf->base);
if(conf->send_msb_first)
spi_send_msb_first(conf->base);
else
spi_send_lsb_first(conf->base);
spi_set_nss_high(conf->base);
#endif
/* Set up device struct */
spi->base = conf->base;
spi->irq = conf->irq;
//spi->tx_dma_config = &conf->tx_dma;
//spi->rx_dma_config = &conf->rx_dma;
spi->mutex = mutex_init();
/* Store address in the DEV_SPI array. */
DEV_SPI[conf->idx] = spi;
/* Enable interrupts */
//nvic_set_priority(conf->irq, 1);
//nvic_enable_irq(conf->irq);
return 0;
}
