static rt_err_t wm_hostspi_init(struct rt_spi_configuration *cfg)
{
spi_clear_fifo();
spi_set_endian(1);
if (cfg->data_width == 8)
{
tls_spi_trans_type(SPI_BYTE_TRANSFER);
}
if (cfg->data_width == 16)
{
tls_spi_trans_type(SPI_WORD_TRANSFER);
}
spi_set_mode(cfg->mode);
spi_set_chipselect_mode(SPI_CS_INACTIVE_MODE);
spi_force_cs_out(1);
if(cfg->max_hz > BSP_SPI_MAX_HZ)
{
cfg->max_hz = BSP_SPI_MAX_HZ;
}
spi_set_sclk(cfg->max_hz);
spi_set_tx_trigger_level(0);
spi_set_rx_trigger_level(7);
spi_set_rx_channel(1);
spi_set_tx_channel(1);
return RT_EOK;
}
esp_err_t spi_init(spi_host_t host, spi_config_t *config)
{
SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
SPI_CHECK(host > CSPI_HOST, "CSPI_HOST can't support now", ESP_FAIL);
SPI_CHECK(NULL == spi_object[host], "spi has been initialized", ESP_FAIL);
spi_object[host] = (spi_object_t *)malloc(sizeof(spi_object_t));
SPI_CHECK(spi_object[host], "malloc fail", ESP_ERR_NO_MEM);
spi_object[host]->trans_mux = xSemaphoreCreateMutex();
if (NULL == spi_object[host]->trans_mux) {
spi_deinit(host);
SPI_CHECK(false, "Semaphore create fail", ESP_ERR_NO_MEM);
}
uint16_t dummy_bitlen = 0;
spi_set_event_callback(host, &config->event_cb);
spi_set_mode(host, &config->mode);
spi_set_interface(host, &config->interface);
spi_set_clk_div(host, &config->clk_div);
spi_set_dummy(host, &dummy_bitlen);
spi_set_intr_enable(host, &config->intr_enable);
spi_intr_register(spi_intr, NULL);
spi_intr_enable();
if (spi_object[host]->event_cb) {
spi_object[host]->event_cb(SPI_INIT_EVENT, NULL);
}
return ESP_OK;
}
/**
* \brief Read from the FRAM chip.
* \param address The index of the byte to start reading from.
* \param len The number of bytes to read.
* \param buf A buffer to put the return data in.
* \return 0 on success, -1 on error
*
* Reads len bytes from the FRAM chip starting at address.
*/
int
fm25v02_read(uint16_t address, uint16_t len, uint8_t *buf)
{
uint16_t i;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
/* Send the READ command and the address to the FRAM */
SPI_WRITE(FM25V02_READ_COMMAND);
address &= 0x7fff;
SPI_WRITE((address&0xff00)>>8);
SPI_WRITE((address&0xff));
SPI_FLUSH();
for (i=0; i<len; i++) {
SPI_READ(buf[i]);
}
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
return 0;
}
/**
* \brief Read from the FRAM chip.
* \param address The index of the byte to start reading from.
* \param len The number of bytes to read.
* \param buf A buffer to put the return data in.
* \return 0 on success, -1 on error
*
* Reads len bytes from the FRAM chip starting at address.
*/
int
fm25lb_read(uint16_t address, uint16_t len, uint8_t *buf)
{
uint16_t i;
// uint16_t c;
// uint16_t cycles = (len / 6) + 1;
// uint16_t index = 0;
uint16_t current_address = address;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
SPI_CS_CLR(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
/* Send the READ command and the address to the FRAM */
SPI_WRITE(FM25LB_ADD_ADDRESS_BIT(current_address, FM25LB_READ_COMMAND));
SPI_WRITE(current_address & 0xFF);
SPI_FLUSH();
for (i=0; i<len; i++) {
SPI_READ(buf[i]);
}
SPI_CS_SET(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
return 0;
}
/**
* \brief Write to the FRAM chip.
* \param address The index of the byte to start writing to.
* \param len The number of bytes to write.
* \param buf A buffer of values to write.
* \return 0 on success, -1 on error
*
* Writes len bytes to the FRAM chip starting at address.
*/
int
fm25lb_write(uint16_t address, uint16_t len, uint8_t *buf)
{
uint16_t i;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
SPI_CS_CLR(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
/* Send the WRITE ENABLE command to allow writing to the FRAM */
SPI_WRITE(FM25LB_WRITE_ENABLE_COMMAND);
SPI_CS_SET(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
SPI_CS_CLR(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
/* Send the WRITE command and the address to the FRAM */
SPI_WRITE(FM25LB_ADD_ADDRESS_BIT(address, FM25LB_WRITE_COMMAND));
SPI_WRITE(address & 0xFF);
/* Send the data to write */
for(i=0; i<len; i++) {
SPI_WRITE(buf[i]);
}
SPI_CS_SET(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
return 0;
}
/**
* \brief Write to the FRAM chip.
* \param address The index of the byte to start writing to.
* \param len The number of bytes to write.
* \param buf A buffer of values to write.
* \return 0 on success, -1 on error
*
* Writes len bytes to the FRAM chip starting at address.
*/
int
fm25v02_write(uint16_t address, uint16_t len, uint8_t *buf)
{
uint16_t i;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
/* Send the WRITE ENABLE command to allow writing to the FRAM */
SPI_WRITE(FM25V02_WRITE_ENABLE_COMMAND);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
/* Send the WRITE command and the address to the FRAM */
SPI_WRITE(FM25V02_WRITE_COMMAND);
address &= 0x7fff;
SPI_WRITE((address&0xff00)>>8);
SPI_WRITE((address&0xff));
/* Send the data to write */
for(i=0; i<len; i++) {
SPI_WRITE(buf[i]);
}
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
return 0;
}
/*---------------------------------------------------------------------------*/
void
enc28j60_arch_spi_init(void)
{
spi_init();
spi_cs_init(SPI_CS_PORT, SPI_CS_PIN);
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
}
// SPI init
void spi_init(const unsigned char mode) {
// enable spi pio
spi_pio_enable();
// configure pmc to enabling spi clock
pmc_periph_clock_enable(AT91C_ID_SPI);
// configure spi in current mode
spi_set_mode(mode);
}
void spi_init(_Bool isMsb, spi_op_mode_t opMode, spi_mode_t mode,
spi_prescaler_t scaler)
{
spi_set_msb_lsb(isMsb);
spi_set_operation_mode(opMode);
spi_set_prescaler(scaler);
spi_set_mode(mode);
spi_enable();
}
/*!
* This function configures the hardware SPI for the currrent client.
* Lock must be taken
*
* @param mod the module number
* @param client_config client hardware configuration.
* @return This function returns 0 if successful, -EPERM otherwise.
*/
static int spi_hard_config(module_nb_t mod, spi_config * client_config)
{
int error = 0;
error = spi_set_baudrate(mod, client_config->bit_rate);
if (error < 0) {
return error;
}
spi_set_transfer_length(mod, client_config->bit_count);
error = spi_select_ss(mod, client_config->ss_asserted);
if (error < 0) {
return error;
}
if (client_config->master_mode == true) {
spi_set_mode(mod, SPI_MASTER);
} else {
spi_set_mode(mod, SPI_SLAVE);
}
if (client_config->active_high_ss_polarity == true) {
spi_set_ss_polarity(mod, SPI_SS_ACTIVE_HIGH);
} else {
spi_set_ss_polarity(mod, SPI_SS_ACTIVE_LOW);
}
if (client_config->ss_low_between_bursts == true) {
spi_set_ss_waveform(mod, SPI_LOW_BTN_BURST);
} else {
spi_set_ss_waveform(mod, SPI_PULSE_BTN_BURST);
}
if (client_config->phase == true) {
spi_set_phase(mod, SPI_PHASE_1);
} else {
spi_set_phase(mod, SPI_PHASE_0);
}
if (client_config->active_high_polarity == true) {
spi_set_polarity(mod, SPI_POLARITY_ACTIVE_HIGH);
} else {
spi_set_polarity(mod, SPI_POLARITY_ACTIVE_LOW);
}
return 0;
}
uint8_t fm25v02_readStatus(){
uint8_t statusReg;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_READ_STATUS_COMMAND);
SPI_FLUSH();
SPI_READ(statusReg);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
return statusReg;
}
void fm25v02_dummyWakeup(){
uint8_t dummyReg;
//uint16_t dummyCnt;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
// Delay for 400-ish us
clock_delay_usec(400);
//for (dummyCnt=0; dummyCnt<800; dummyCnt++)
// asm("nop");
SPI_FLUSH();
SPI_READ(dummyReg);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
}
int fm25v02_writeStatus(uint8_t statusReg){
// Set WEL bit in status register
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_WRITE_ENABLE_COMMAND);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_WRITE_STATUS_COMMAND);
SPI_WRITE(statusReg);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
return 0;
}
void nrf51822_get_all_advertisements () {
//spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(NRF51822_CS_N_PORT_NUM, NRF51822_CS_N_PIN);
clock_delay_usec(8);
// GET ADVERTISEMENTS
SPI_WRITE(0x02);
SPI_FLUSH();
SPI_CS_SET(NRF51822_CS_N_PORT_NUM, NRF51822_CS_N_PIN);
}
void
nxt_spi_write(U32 CD, const U8 *data, U32 nBytes)
{
U32 status;
U32 cd_mask = (CD ? 0x100 : 0);
spi_set_mode(CD);
while (nBytes) {
*AT91C_SPI_TDR = (*data | cd_mask);
data++;
nBytes--;
/* Wait until byte sent */
do {
status = *AT91C_SPI_SR;
} while (!(status & 0x200));
}
}
void nrf51822_interrupt(uint8_t port, uint8_t pin)
{
uint16_t b;
uint8_t buf[256];
int i;
leds_toggle(LEDS_RED);
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(NRF51822_CS_N_PORT_NUM, NRF51822_CS_N_PIN);
clock_delay_usec(8);
// READ_IRQ
SPI_WRITE(0x01);
SPI_FLUSH();
SPI_CS_SET(NRF51822_CS_N_PORT_NUM, NRF51822_CS_N_PIN);
clock_delay_usec(75);
SPI_CS_CLR(NRF51822_CS_N_PORT_NUM, NRF51822_CS_N_PIN);
clock_delay_usec(8);
SPI_READ(b);
if (b == 0xFF) {
// ERROR on the nrf51822 side. Skip this.
} else {
for (i=0; i<b; i++) {
SPI_READ(buf[i]);
}
}
SPI_CS_SET(NRF51822_CS_N_PORT_NUM, NRF51822_CS_N_PIN);
}
void fm25v02_eraseAll(){
uint16_t i;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_WRITE_ENABLE_COMMAND);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_WRITE_COMMAND);
// Address
SPI_WRITE(0x00);
SPI_WRITE(0x00);
/* Send the data to write */
for(i=0; i<0x7fff; i++) {
SPI_WRITE(0x00);
}
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
}
/*---------------------------------------------------------------------------*/
PROCESS_THREAD(main_process, ev, data)
{
PROCESS_BEGIN();
INIT_NETWORK_DEBUG();
{
static struct etimer et;
PRINTF("=====Start=====\n");
spi_init();
spi_set_mode(MIKROBUS_1, SPI_MODE_0);
if (eve_click_enable(MIKROBUS_1) < 0)
return -1;
/* Display a green screen for 3 seconds */
eve_click_clear(0, 255, 0);
eve_click_display();
etimer_set(&et, CLOCK_SECOND);
PROCESS_WAIT_EVENT();
/* Display some text */
eve_click_clear(0, 0, 0); /* black screen */
eve_click_draw(FT800_TEXT,
240, /* x */
136, /* y */
31, /* font */
FT800_OPT_CENTER, /* options */
"Hello World !");
eve_click_display();
etimer_set(&et, CLOCK_SECOND);
PROCESS_WAIT_EVENT();
eve_click_disable(MIKROBUS_1);
spi_release();
}
PROCESS_END();
}
static void spi_setup(void)
{
/* Enable GPIOB clock. */
rcc_enable_clock(RCC_GPIOB);
/* 'nRST' LOW */
gpio_clear(GPIO_PB11);
/* Set GPIO11 (in GPIO port B) to 'output push-pull'. */
gpio_config_output(GPIO_PUSHPULL, GPIO_40MHZ, GPIO_NOPUPD, GPIO_PB11);
/* Enable SPI2 clock. */
rcc_enable_clock(RCC_SPI2);
/* Set GPIO13, 15 (in GPIO port B) to 'altfn push-pull'. */
gpio_config_altfn(GPIO_SPI1_2, GPIO_PUSHPULL, GPIO_40MHZ, GPIO_NOPUPD,
GPIO_PB(SPI2_SCK, SPI2_MOSI));
/* Set SPI mode (32 / 4 = 8MHz). */
spi_set_mode(SPI2, 4, SPI_16BIT | SPI_LSB_FIRST | SPI_NSS_SOFTWARE |
SPI_NSS_HIGH | SPI_MASTER | SPI_ENABLE);
}
void spi_master_setup_device(volatile avr32_spi_t *spi,
struct spi_device *device, spi_flags_t flags, uint32_t baud_rate,
board_spi_select_id_t sel_id)
{
spi_set_chipselect_delay_bct(spi,device->id,CONFIG_SPI_MASTER_DELAY_BCT);
spi_set_chipselect_delay_bs(spi,device->id,CONFIG_SPI_MASTER_DELAY_BS);
spi_set_bits_per_transfer(spi,device->id,
CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
spi_set_baudrate_register(spi,device->id,
getBaudDiv(baud_rate, sysclk_get_peripheral_bus_hz(spi)));
spi_enable_active_mode(spi,device->id);
spi_set_mode(spi,device->id,flags);
#ifdef FREERTOS_USED
if (!xSPIMutex) {
// Create the SPI mutex.
vSemaphoreCreateBinary(xSPIMutex);
if (!xSPIMutex) {
while(1);
}
}
#endif
}
void
spi_isr_C(void)
{
if (page == 0)
{
/* Check to see if we have data to display */
if (dirty != 0)
{
data = display;
dirty = 0;
}
else
{
/* No so turn things off. It will get re-set if we ever have anything
to display
*/
*AT91C_SPI_IDR = AT91C_SPI_ENDTX;
return;
}
}
/* Make sure we are in data mode */
spi_set_mode(1);
/* now do the transfer. We make use of the auto-wrap function so simply
* need to send 8*132 bytes to get back to where we started. However the
* display buffer is structured as series of 100 byte lines, so we need to
* get tricky. I've made the display one line longer (9 lines) and so when we
* send the data we send 100 bytes from the actual line plus 32 padding bytes
* (that are not actually seen), from the next line. The extra line means
* that this is safe to do. If we can redefine the display as a 8*132 then
* we could just use a single dma transfer (instead of 8, 132 byte ones).
* However I'm not sure if this would be safe.
*/
*AT91C_SPI_TNPR = (U32) data;
*AT91C_SPI_TNCR = 132;
page = (page + 1) % 8;
data += 100;
}
SD::SD()
{
uint8_t retry = 0;
/* Setup pins direction */
spi_set_master_port_dir(SD_PORT);
#ifdef COMPILE_SD_INSERT_DETECT
/* Setup SD switch pin */
SD_PORT.DIRCLR = 1<<SD_SWITCH_PIN;
SD_PORT.INT0MASK = 1<<SD_SWITCH_PIN;
SD_PORT.INTCTRL = PORT_INT0LVL_LO_gc;
SD_PORT.PIN1CTRL = PORT_ISC_BOTHEDGES_gc|PORT_OPC_PULLUP_gc;
#endif
spi_cs_disable(SD_PORT);
spi_set_mode(SD_SPI,SPI_MODE_0_gc);
spi_set_dord(SD_SPI,SPI_DORD_MSB_FIRST);
spi_enable_master(SD_SPI);
while ((retry++<10) && !m_bCardInitialized) {Init();}
}
void fm25v02_sleep(){
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_SLEEP_COMMAND);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
}
/**
MFRC522::MFRC522()
{
/* Set Reset pin */
MFRC522_PORT.OUTCLR = 1<<MFRC522_RESET_PIN; /* Reset on */
MFRC522_PORT.DIRSET = 1<<MFRC522_RESET_PIN; /* Set as output */
MFRC522_PORT.OUTSET = 1<<MFRC522_RESET_PIN; /* Reset off */
/* Setup SPI driver */
spi_set_master_port_dir(MFRC522_PORT);
spi_cs_disable(MFRC522_PORT);
spi_set_mode(MFRC522_SPI,SPI_MODE_0_gc);
spi_set_dord(MFRC522_SPI,SPI_DORD_MSB_FIRST);
spi_enable_master(MFRC522_SPI);
/* Set SPI Baudrate */
#if (MFRC522_BAUD <= F_CPU/128)
MFRC522_SPI.CTRL |= SPI_PRESCALER_DIV128_gc;
#elif (MFRC522_BAUD <= F_CPU/64)
MFRC522_SPI.CTRL |= SPI_PRESCALER_DIV64_gc;
#elif (MFRC522_BAUD <= F_CPU/32)
MFRC522_SPI.CTRL |= 1<<SPI_CLK2X_bp|SPI_PRESCALER_DIV64_gc;
#elif (MFRC522_BAUD <= F_CPU/16)
MFRC522_SPI.CTRL |= SPI_PRESCALER_DIV16_gc;
#elif (MFRC522_BAUD <= F_CPU/8)
MFRC522_SPI.CTRL |= 1<<SPI_CLK2X_bp|SPI_PRESCALER_DIV16_gc;
#elif (MFRC522_BAUD <= F_CPU/4)
MFRC522_SPI.CTRL |= SPI_PRESCALER_DIV4_gc;
#elif (MFRC522_BAUD <= F_CPU/2)
MFRC522_SPI.CTRL |= 1<<SPI_CLK2X_bp|SPI_PRESCALER_DIV4_gc;
#else
MFRC522_SPI.CTRL |= 1<<SPI_CLK2X_bp|SPI_PRESCALER_DIV4_gc;
#endif
/* Set interrupt on pin MFRC522_IRQ_PIN */
MFRC522_PORT.INT0MASK = 1<<MFRC522_IRQ_PIN;
MFRC522_PORT.INTCTRL = PORT_INT0LVL_HI_gc;
#if MFRC522_IRQ_PIN == 0
MFRC522_PORT.PIN0CTRL = PORT_ISC_FALLING_gc|PORT_OPC_PULLUP_gc;
#elif MFRC522_IRQ_PIN == 1
MFRC522_PORT.PIN1CTRL = PORT_ISC_FALLING_gc|PORT_OPC_PULLUP_gc;
#elif MFRC522_IRQ_PIN == 2
MFRC522_PORT.PIN2CTRL = PORT_ISC_FALLING_gc|PORT_OPC_PULLUP_gc;
#elif MFRC522_IRQ_PIN == 3
MFRC522_PORT.PIN3CTRL = PORT_ISC_FALLING_gc|PORT_OPC_PULLUP_gc;
#elif MFRC522_IRQ_PIN == 4
MFRC522_PORT.PIN4CTRL = PORT_ISC_FALLING_gc|PORT_OPC_PULLUP_gc;
#elif MFRC522_IRQ_PIN == 5
MFRC522_PORT.PIN5CTRL = PORT_ISC_FALLING_gc|PORT_OPC_PULLUP_gc;
#elif MFRC522_IRQ_PIN == 6
MFRC522_PORT.PIN6CTRL = PORT_ISC_FALLING_gc|PORT_OPC_PULLUP_gc;
#elif MFRC522_IRQ_PIN == 7
MFRC522_PORT.PIN7CTRL = PORT_ISC_FALLING_gc|PORT_OPC_PULLUP_gc;
#endif
for (uint16_t i=0; i<0x7FFF; i++); /* Wait routine until oscillator is ready. t >= 37.74us */
WriteReg(REG_CommandReg,COMM_SoftReset); /* Soft Reset */
WriteReg(REG_TModeReg, 0x80); /* TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds */
WriteReg(REG_TPrescalerReg, 0xA9); /* TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us. */
WriteReg(REG_TReloadRegH, 0x03); /* Reload timer with 0x3E8 = 1000, ie 25ms before timeout. */
WriteReg(REG_TReloadRegL, 0xe8);
WriteReg(REG_TxASKReg, 0x40); /* Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting */
WriteReg(REG_ModeReg, 0x3D); /* Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4) */
AntennaOn();
}
static int lua_spi_newindex(lua_State *L) {
spi_t *spi;
const char *field;
spi = luaL_checkudata(L, 1, "periphery.SPI");
if (!lua_isstring(L, 2))
return lua_spi_error(L, SPI_ERROR_ARG, 0, "Error: unknown property");
field = lua_tostring(L, 2);
if (strcmp(field, "fd") == 0)
return lua_spi_error(L, SPI_ERROR_ARG, 0, "Error: immutable property");
else if (strcmp(field, "mode") == 0) {
unsigned int mode;
int ret;
lua_spi_checktype(L, 3, LUA_TNUMBER);
mode = lua_tounsigned(L, 3);
if ((ret = spi_set_mode(spi, mode)) < 0)
return lua_spi_error(L, ret, spi_errno(spi), "Error: %s", spi_errmsg(spi));
return 0;
} else if (strcmp(field, "max_speed") == 0) {
uint32_t max_speed;
int ret;
lua_spi_checktype(L, 3, LUA_TNUMBER);
max_speed = lua_tounsigned(L, 3);
if ((ret = spi_set_max_speed(spi, max_speed)) < 0)
return lua_spi_error(L, ret, spi_errno(spi), "Error: %s", spi_errmsg(spi));
return 0;
} else if (strcmp(field, "bit_order") == 0) {
const char *s;
spi_bit_order_t bit_order;
int ret;
lua_spi_checktype(L, 3, LUA_TSTRING);
s = lua_tostring(L, 3);
if (strcmp(s, "msb") == 0)
bit_order = MSB_FIRST;
else if (strcmp(s, "lsb") == 0)
bit_order = LSB_FIRST;
else
return lua_spi_error(L, SPI_ERROR_ARG, 0, "Error: invalid bit_order, should be 'msb' or 'lsb'");
if ((ret = spi_set_bit_order(spi, bit_order)) < 0)
return lua_spi_error(L, ret, spi_errno(spi), "Error: %s", spi_errmsg(spi));
return 0;
} else if (strcmp(field, "bits_per_word") == 0) {
uint8_t bits_per_word;
int ret;
lua_spi_checktype(L, 3, LUA_TNUMBER);
bits_per_word = lua_tounsigned(L, 3);
if ((ret = spi_set_bits_per_word(spi, bits_per_word)) < 0)
return lua_spi_error(L, ret, spi_errno(spi), "Error: %s", spi_errmsg(spi));
return 0;
} else if (strcmp(field, "extra_flags") == 0) {
uint8_t extra_flags;
int ret;
lua_spi_checktype(L, 3, LUA_TNUMBER);
extra_flags = lua_tounsigned(L, 3);
if ((ret = spi_set_extra_flags(spi, extra_flags)) < 0)
return lua_spi_error(L, ret, spi_errno(spi), "Error: %s", spi_errmsg(spi));
return 0;
}
return lua_spi_error(L, SPI_ERROR_ARG, 0, "Error: unknown property");
}
/*
* BLSP QUPn SPI Hardware Initialisation
*/
static int spi_hw_init(struct ipq_spi_slave *ds)
{
int ret;
ds->initialized = 0;
/* QUPn module configuration */
spi_reset(ds);
/* Set the QUPn state */
ret = config_spi_state(ds, QUP_STATE_RESET);
if (ret)
return ret;
/*
* Configure Mini core to SPI core with Input Output enabled,
* SPI master, N = 8 bits
*/
clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
QUP_CONF_INPUT_MSK |
QUP_CONF_OUTPUT_MSK |
QUP_CONF_N_MASK,
QUP_CONFIG_MINI_CORE_SPI |
QUP_CONF_INPUT_ENA |
QUP_CONF_OUTPUT_ENA |
QUP_CONF_N_SPI_8_BIT_WORD);
/*
* Configure Input first SPI protocol,
* SPI master mode and no loopback
*/
clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
SPI_CONFIG_NO_SLAVE_OPER_MSK,
SPI_CONFIG_NO_LOOP_BACK |
SPI_CONFIG_NO_SLAVE_OPER);
/*
* Configure SPI IO Control Register
* CLK_ALWAYS_ON = 0
* MX_CS_MODE = 0
* NO_TRI_STATE = 1
*/
write32(ds->regs->io_control, SPI_IO_CTRL_CLK_ALWAYS_ON |
SPI_IO_CTRL_NO_TRI_STATE);
/*
* Configure SPI IO Modes.
* OUTPUT_BIT_SHIFT_EN = 1
* INPUT_MODE = Block Mode
* OUTPUT MODE = Block Mode
*/
clrsetbits_le32(ds->regs->qup_io_modes,
QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK |
QUP_IO_MODES_INPUT_MODE_MSK |
QUP_IO_MODES_OUTPUT_MODE_MSK,
QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN |
QUP_IO_MODES_INPUT_BLOCK_MODE |
QUP_IO_MODES_OUTPUT_BLOCK_MODE);
spi_set_mode(ds, ds->mode);
/* Disable Error mask */
write32(ds->regs->error_flags_en, 0);
write32(ds->regs->qup_error_flags_en, 0);
write32(ds->regs->qup_deassert_wait, 0);
ds->initialized = 1;
return SUCCESS;
}
