/*----------------------------------------------------------------------------
Initialize SPIFI API & Pins
*----------------------------------------------------------------------------*/
void SPIFI_Init (void) {
#ifdef USE_SPIFI_LIB
/* Use spifi function names directly */
#else
SPIFI_RTNS * pSpifi;
pSpifi = (SPIFI_RTNS *)(SPIFI_ROM_PTR);
/* Call functions via spifi rom table */
#define spifi_init pSpifi->spifi_init
#endif
/* init SPIFI clock and pins */
LPC_SC->PCONP |= (1UL << 16); /* enable SPIFI power/clock */
LPC_IOCON->P2_7 &= ~(7UL << 0);
LPC_IOCON->P2_7 |= (5UL << 0); /* SPIFI_CSN = P2.7 (FUNC 5) */
LPC_IOCON->P0_22 &= ~(7UL << 0);
LPC_IOCON->P0_22 |= (5UL << 0); /* SPIFI_CLK = P0.22 (FUNC 5) */
LPC_IOCON->P0_15 &= ~(7UL << 0);
LPC_IOCON->P0_15 |= (5UL << 0); /* SPIFI_IO2 = P0.15 (FUNC 5) */
LPC_IOCON->P0_16 &= ~(7UL << 0);
LPC_IOCON->P0_16 |= (5UL << 0); /* SPIFI_IO3 = P0.16 (FUNC 5) */
LPC_IOCON->P0_17 &= ~(7UL << 0);
LPC_IOCON->P0_17 |= (5UL << 0); /* SPIFI_IO1 = P0.17 (FUNC 5) */
LPC_IOCON->P0_18 &= ~(7UL << 0);
LPC_IOCON->P0_18 |= (5UL << 0); /* SPIFI_IO0 = P0.18 (FUNC 5) */
if (spifi_init(&obj, 3, S_RCVCLK | S_FULLCLK, 48)) {
while (1);
}
}
/**
* @brief Main entry point
* @return Nothing
*/
int main(void)
{
SPIFIobj *obj = &spifi_obj;
uint32_t spifi_clk_mhz;
SPIFIopers opers;
int ret;
spifi_rom_init(spifi);
/* Initialize the board & LEDs for error indication */
Board_Init();
/* Since this code runs from SPIFI no special initialization required here */
prepare_write_data(data_buffer, sizeof(data_buffer));
spifi_clk_mhz = Chip_Clock_GetRate(CLK_MX_SPIFI) / 1000000;
/* Typical time tCS is 20 ns min, we give 200 ns to be on safer side */
if (spifi_init(obj, spifi_clk_mhz / 5, S_RCVCLK | S_FULLCLK, spifi_clk_mhz)) {
DEBUGSTR("Error initializing SPIFI interface!\r\n");
Board_LED_Set(1, 1);
goto end_prog;
}
/* Prepare the operations structure */
memset(&opers, 0, sizeof(SPIFIopers));
opers.dest = (char *) SPIFI_WRITE_SECTOR_OFFSET;
opers.length = sizeof(data_buffer);
/* opers.options = S_VERIFY_PROG; */
/* NOTE: All interrupts must be disabled before calling program as
* any triggered interrupts might attempt to run a code from SPIFI area
*/
ret = spifi_program(obj, (char *) data_buffer, &opers);
if (ret) {
DEBUGOUT("Error 0x%x: Programming of data buffer to SPIFI Failed!\r\n", ret);
Board_LED_Set(1, 1);
goto end_prog;
}
DEBUGSTR("SPIFI Programming successful!\r\n");
if (verify_spifi_data((uint8_t *) SPIFI_WRITE_SECTOR_ADDRESS, sizeof(data_buffer))) {
DEBUGSTR("Error verifying the SPIFI data\r\n");
Board_LED_Set(1, 1);
goto end_prog;
}
Board_LED_Set(0, 1);
DEBUGSTR("SPIFI Data verified!\r\n");
end_prog:
while(1) {__WFI();}
}
void clockInit(void)
{
//uint32_t EMCClk;
__disable_irq();
/* Set the XTAL oscillator frequency to 12MHz*/
CGU_SetXTALOSC(__CRYSTAL);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
/* Set PL160M 12*1 = 12 MHz */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
// CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_CLKSRC_PLL1);
CGU_SetPLL1(1);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
// setup CLKOUT
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVB);
CGU_EnableEntity(CGU_CLKSRC_IDIVB, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVB, 12); // 12 -> 6 pclks per cpu clk, 10 -> 5 pclks
// set input for CLKOUT to IDIVB
LPC_CGU->BASE_OUT_CLK &= ~0x0f000000;
LPC_CGU->BASE_OUT_CLK |= 0x0d000000;
/* Run SPIFI from PL160M, /2 */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVA, 2);
CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
CGU_UpdateClock();
LPC_CCU1->CLK_M4_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
LPC_CCU1->CLK_M4_EMC_CFG |= (1<<0); // Turn on clock
/* Set PL160M @ 12*9=108 MHz */
CGU_SetPLL1(9);
/* Run base M3 clock from PL160M, no division */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
waitMS(10);
/* Change the clock to 204 MHz */
/* Set PL160M @ 12*15=180 MHz */
CGU_SetPLL1(17);
waitMS(10);
CGU_UpdateClock();
//EMCFlashInit();
//vEMC_InitSRDRAM(SDRAM_BASE_ADDR, SDRAM_WIDTH, SDRAM_SIZE_MBITS, SDRAM_DATA_BUS_BITS, SDRAM_COL_ADDR_BITS);
LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
/* IO pins */
LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */
#if 0
EMCClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE)/2;
if (spifi_init(&sobj, 9, S_RCVCLK | S_FULLCLK, EMCClk)) {
if (spifi_init(&sobj, 9, S_RCVCLK | S_FULLCLK, EMCClk)) {
while(1);
}
}
#endif
__enable_irq();
// SPIFI_Init();
}
