void spm_module_init(void) { int r; unsigned long flags; struct wd_api *wd_api; spin_lock_irqsave(&spm_lock, flags); /* enable register control */ spm_write(SPM_POWERON_CONFIG_SET, (SPM_PROJECT_CODE << 16) | (1U << 0)); /* init power control register (select PCM clock to 26M) */ spm_write(SPM_POWER_ON_VAL0, 0); spm_write(SPM_POWER_ON_VAL1, 0x00015820); spm_write(SPM_PCM_PWR_IO_EN, 0); /* reset PCM */ spm_write(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); spm_write(SPM_PCM_CON0, CON0_CFG_KEY); /* init PCM control register */ spm_write(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); spm_write(SPM_PCM_CON1, CON1_CFG_KEY | CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_IM_NONRP_EN | CON1_MIF_APBEN); spm_write(SPM_PCM_IM_PTR, 0); spm_write(SPM_PCM_IM_LEN, 0); /* SRCLKENA: POWER_ON_VAL1 (PWR_IO_EN[7]=0) or POWER_ON_VAL1|r7 (PWR_IO_EN[7]=1) */ /* CLKSQ: POWER_ON_VAL0 (PWR_IO_EN[0]=0) or r0 (PWR_IO_EN[0]=1) */ /* SRCLKENAI will trigger 26M-wake/sleep event */ spm_write(SPM_CLK_CON, CC_CXO32K_RM_EN_MD); spm_write(SPM_PCM_SRC_REQ, (1U << 1)); /* clean wakeup event raw status */ spm_write(SPM_SLEEP_WAKEUP_EVENT_MASK, 0xffffffff); /* clean ISR status */ spm_write(SPM_SLEEP_ISR_MASK, ISRM_ALL); spm_write(SPM_SLEEP_ISR_STATUS, ISRC_ALL); spm_write(SPM_PCM_SW_INT_CLEAR, PCM_SW_INT_ALL); spin_unlock_irqrestore(&spm_lock, flags); r = request_irq(MT_SPM_IRQ_ID, spm_irq_handler, IRQF_TRIGGER_LOW | IRQF_NO_SUSPEND, "mt-spm", NULL); if (r) { spm_error("FAILED TO REQUEST SPM IRQ (%d)\n", r); WARN_ON(1); } get_wd_api(&wd_api); if (wd_api->wd_spmwdt_mode_config && wd_api->wd_thermal_mode_config) { wd_api->wd_spmwdt_mode_config(WD_REQ_EN, WD_REQ_RST_MODE); wd_api->wd_thermal_mode_config(WD_REQ_EN, WD_REQ_RST_MODE); } else { spm_error("FAILED TO GET WD API\n"); WARN_ON(1); } spm_go_to_normal(); /* let PCM help to do thermal protection */ }
void spm_module_init(void) { int r; unsigned long flags; spm_fs_init(); spin_lock_irqsave(&spm_lock, flags); #if 1//def SPM_CLOCK_INIT /*Only set during bringup init. No need to be changed.*/ if(clock_is_on(MT_CG_SPM_52M_SW_CG)) disable_clock(MT_CG_SPM_52M_SW_CG, "SPM"); if(!clock_is_on(MT_CG_SC_26M_CK_SEL_EN)) enable_clock(MT_CG_SC_26M_CK_SEL_EN, "SPM");//Enable the feature that SPM can switch bus and audio clock to be 26Mhz if(clock_is_on(MT_CG_SC_MEM_CK_OFF_EN)) disable_clock(MT_CG_SC_MEM_CK_OFF_EN, "SPM"); /*Dynamic on/off before entering suspend/DPidle and after leaving suspend/DPidle*/ if(!clock_is_on(MT_CG_MEMSLP_DLYER_SW_CG)) enable_clock(MT_CG_MEMSLP_DLYER_SW_CG, "SPM"); if(!clock_is_on(MT_CG_SPM_SW_CG))//need check with mtcmos owner for spm clk init gating enable_clock(MT_CG_SPM_SW_CG, "SPM"); #endif spin_unlock_irqrestore(&spm_lock, flags); r = request_irq(MT_SPM0_IRQ_ID, spm0_irq_handler, IRQF_TRIGGER_LOW,"mt-spm", NULL); if (r) { spm_error("SPM IRQ[0] register failed (%d)\n", r); WARN_ON(1); } #ifdef CONFIG_KICK_SPM_WDT #ifndef CONFIG_FIQ_GLUE //printk("******** MTK WDT register irq ********\n" ); r = request_irq(MT_SPM1_IRQ_ID, spm1_irq_handler, IRQF_TRIGGER_LOW,"[SPM WDT]", NULL); #else //printk("******** MTK WDT register fiq ********\n" ); r = request_fiq(MT_SPM1_IRQ_ID, spm1_fiq_handler, IRQF_TRIGGER_LOW, NULL); #endif #else r = request_irq(MT_SPM1_IRQ_ID, spm1_irq_handler, IRQF_TRIGGER_LOW,"mt-spm", NULL); #endif if (r) { spm_error("SPM IRQ[1] register failed (%d)\n", r); WARN_ON(1);} }
static irqreturn_t spm_irq_handler(int irq, void *dev_id) { u32 isr; twam_sig_t twamsig; spin_lock(&spm_lock); /* get ISR status */ isr = spm_read(SPM_SLEEP_ISR_STATUS); if (isr & ISR_TWAM) { twamsig.sig0 = spm_read(SPM_SLEEP_TWAM_STATUS0); twamsig.sig1 = spm_read(SPM_SLEEP_TWAM_STATUS1); twamsig.sig2 = spm_read(SPM_SLEEP_TWAM_STATUS2); twamsig.sig3 = spm_read(SPM_SLEEP_TWAM_STATUS3); } /* clean ISR status */ spm_write(SPM_SLEEP_ISR_MASK, spm_read(SPM_SLEEP_ISR_MASK) | ISRM_ALL_EXC_TWAM); spm_write(SPM_SLEEP_ISR_STATUS, isr); if (isr & ISR_TWAM) udelay(100); /* need 3T TWAM clock */ spm_write(SPM_PCM_SW_INT_CLEAR, PCM_SW_INT0); spin_unlock(&spm_lock); if (isr == ISR_TWAM && spm_twam_handler) spm_twam_handler(&twamsig); else spm_error("ISR SHOULD NOT BE EXECUTED (0x%x)\n", isr); return IRQ_HANDLED; }
void spm_fiq_wdt_woof(void *arg, void *regs, void *svc_sp) { int i; for(i=0;i<20;i++){ spm_error("!!!!!![SPM FIQ] WDT WOOF WOOF WOOF!!!!!\n"); mdelay(1); } }
void spm_irq_wdt_woof(int irq, void *dev_id) { int i; for(i=0;i<20;i++){ spm_error("!!!!!![SPM IRQ] WDT WOOF WOOF WOOF!!!!!\n"); mdelay(1); } }
irqreturn_t spm1_irq_handler(int irq, void *dev_id) { #ifdef CONFIG_KICK_SPM_WDT //spin_lock(&spm_lock); spm_error("Orz.Orz.Orz...SPM WDT Timeout @ IRQ\n"); if(spm_wdt_irq_bark) (*spm_wdt_irq_bark)(irq, dev_id); #else spm_error("GENE", "!!! SPM ISR[0] SHOULD NOT BE EXECUTED !!!\n"); spin_lock(&spm_lock); /* clean ISR status */ spm_write(SPM_SLEEP_ISR_MASK, 0x0008); spm_write(SPM_SLEEP_ISR_STATUS, 0x0018); spin_unlock(&spm_lock); #endif return IRQ_HANDLED; }
irqreturn_t spm0_irq_handler(int irq, void *dev_id) { spm_error("!!! SPM ISR[0] SHOULD NOT BE EXECUTED !!!\n"); spin_lock(&spm_lock); /* clean ISR status */ spm_write(SPM_SLEEP_ISR_MASK, 0x0008); spm_write(SPM_SLEEP_ISR_STATUS, 0x0018); spin_unlock(&spm_lock); return IRQ_HANDLED; }
static u32 spm_get_wake_period(wake_reason_t last_wr) { int period; /* battery decreases 1% */ period = get_dynamic_period(!!(last_wr != WR_PCM_TIMER), 600, 1); if (period <= 1) { spm_error("!!! CANNOT GET PERIOD FROM FUEL GAUGE !!!\n"); period = 600; } else if (period > 36 * 3600) { /* max period is 36.4 hours */ period = 36 * 3600; } return period; }