void __sramfunc rk30_pwm_logic_suspend_voltage(void)
{
#ifdef CONFIG_RK30_PWM_REGULATOR
#ifdef CONFIG_MACH_RK2926_M713
sram_udelay(10000);
gpio0d3_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
gpio0d3_do = gpio0_readl(GPIO_SWPORTA_DR);
gpio0d3_dir = gpio0_readl(GPIO_SWPORTA_DDR);
writel_relaxed((gpio0d3_iomux |(1<<22)) & (~(1<<6)), GRF_GPIO0D_IOMUX);
gpio0_writel(gpio0d3_dir |(1<<27), GPIO_SWPORTA_DDR);
gpio0_writel(gpio0d3_do |(1<<27), GPIO_SWPORTA_DR);
#else
// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
sram_udelay(10000);
gpio0d4_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
gpio0d4_do = gpio0_readl(GPIO_SWPORTA_DR);
gpio0d4_dir = gpio0_readl(GPIO_SWPORTA_DDR);
writel_relaxed((gpio0d4_iomux |(1<<24)) & (~(1<<8)), GRF_GPIO0D_IOMUX);
gpio0_writel(gpio0d4_dir |(1<<28), GPIO_SWPORTA_DDR);
gpio0_writel(gpio0d4_do |(1<<28), GPIO_SWPORTA_DR);
#endif
#endif
}
void __sramfunc board_pmu_resume(void)
{
int ret;
ret = gpio_readl(GPIO_SWPORTA_DDR);
gpio_writel(ret | GPIO3_D2_OUTPUT, GPIO_SWPORTA_DDR);
ret = gpio_readl(GPIO_SWPORTA_DR);
gpio_writel(ret & GPIO3_D2_OUTPUT_LOW, GPIO_SWPORTA_DR); //set pmu_sleep output low
sram_udelay(2000);
}
void __sramfunc rk30_pwm_logic_resume_voltage(void)
{
#ifdef CONFIG_RK30_PWM_REGULATOR
#ifdef CONFIG_MACH_RK2926_M713
writel_relaxed((1<<22)|gpio0d3_iomux, GRF_GPIO0D_IOMUX);
gpio0_writel(gpio0d3_dir, GPIO_SWPORTA_DDR);
gpio0_writel(gpio0d3_do, GPIO_SWPORTA_DR);
sram_udelay(10000);
#else
writel_relaxed((1<<24)|gpio0d4_iomux, GRF_GPIO0D_IOMUX);
gpio0_writel(gpio0d4_dir, GPIO_SWPORTA_DDR);
gpio0_writel(gpio0d4_do, GPIO_SWPORTA_DR);
sram_udelay(10000);
#endif
#endif
}
void __sramfunc board_pmu_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output high
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
#ifdef CONFIG_CLK_SWITCH_TO_32K
sram_32k_udelay(10000);
#else
sram_udelay(10000);
#endif
}
void __sramfunc board_pmu_tps65910_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
#ifdef CONFIG_CLK_SWITCH_TO_32K //switch clk to 24M
sram_32k_udelay(10000);
#else
sram_udelay(2000);
#endif
}
void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
{
uint8 slaveaddr;
uint8 slavereg;
uint8 data,ret = 0;
#if defined ( CONFIG_ARCH_RK3026)
uint8 data2;
data2 = logic_voltage;
#endif
data = arm_voltage;
sram_i2c_init(); //init i2c device
#if defined(CONFIG_MFD_TPS65910)
if(pmic_is_tps65910())
{
slaveaddr = 0x2d; //slave device addr
slavereg = 0x22; // reg add
sram_i2c_write(slaveaddr, slavereg, data);
sram_udelay(20000);
#if defined ( CONFIG_ARCH_RK3026)
sram_i2c_write(slaveaddr, 0x25, data2);
sram_udelay(20000);
#endif
}
#endif
#if defined(CONFIG_REGULATOR_ACT8931)
if(pmic_is_act8931())
{
slaveaddr = 0x5b; //slave device addr
slavereg = 0x40; // reg addr
sram_i2c_write(slaveaddr, slavereg, data);
sram_i2c_write(slaveaddr, (slavereg+0x1), data);
sram_udelay(20000);
}
#endif
sram_i2c_deinit(); //deinit i2c device
}
void __sramfunc sram_i2c_get_ipd_event(int type)
{
int time = 2000;
unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
writel_relaxed(type, SRAM_I2C_ADDRBASE + I2C_IEN);
do{
sram_udelay(10);
con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
}while(((--time) & (~(con & type))));
writel_relaxed(type,SRAM_I2C_ADDRBASE + I2C_IPD);
if(time <= 0){
sram_printch('T');
}
}
void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
{
sram_i2c_init();
#if defined(CONFIG_KP_AXP22)
#if defined(CONFIG_CLK_SWITCH_TO_GND)
if (sram_pm_state == PM_SUSPEND_MEM)
{
#if defined(CONFIG_MACH_RK3026_E602)
//aldo3 VCCA_3V3
sram_i2c_write(0x34, 0x13, 0x80);
#endif
axpreg12 &= (~0x10); /*close dldo2 for sleep control*/
sram_i2c_write(0x34, 0x12, axpreg12);
}
#endif
sram_i2c_write(0x34, 0x22, arm_voltage);
sram_i2c_write(0x34, 0x23, vcode_voltage);
sram_i2c_write(0x34, 0x25, vddr_voltage);
#endif
#if defined(CONFIG_REGULATOR_ACT8931)
uint8 slaveaddr;
uint8 slavereg;
uint8 data;
slaveaddr = 0x5b;
#if defined(CONFIG_CLK_SWITCH_TO_GND)
if (sram_pm_state == PM_SUSPEND_MEM)
{//LDO2
slavereg = 0x55;
data = 0x41; //ldo disable
sram_i2c_write(slaveaddr, slavereg, data);
}
#endif
{//ARM
slavereg = 0x40;
data = arm_voltage;
sram_i2c_write(slaveaddr, slavereg, data);
sram_i2c_write(slaveaddr, (slavereg+0x1), data);
sram_udelay(20000);
}
#endif
sram_i2c_deinit();
}
