/* ********************************************************************************************************* * standby_power_init * * Description: init power for standby. * * Arguments : none; * * Returns : result; ********************************************************************************************************* */ __s32 standby_power_init(void) { __u8 val, mask, reg_val; __s32 i; standby_twi_init(AXP_IICBUS); #if(AXP_WAKEUP & AXP_WAKEUP_KEY) /* enable pek long/short */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN3, ®_val); reg_val |= 0x03; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN3, ®_val); #endif #if(AXP_WAKEUP & AXP_WAKEUP_LOWBATT) /* enable low voltage warning */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN4, ®_val); reg_val |= 0x03; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN4, ®_val); /* clear pending */ reg_val = 0x03; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQ4, ®_val); #endif return 0; }
void standby_enter_low(void) { /*sdram self-refresh*/ aw_writel(aw_readl(SW_DRAM_SDR_CTL_REG)|SDR_ENTER_SELFRFH,SW_DRAM_SDR_CTL_REG); while(!(aw_readl(SW_DRAM_SDR_CTL_REG)&SDR_SELFRFH_STATUS)); /*gate off sdram*/ aw_writel(aw_readl(SW_CCM_SDRAM_PLL_REG)&~SDR_CLOCK_GATE_EN,SW_CCM_SDRAM_PLL_REG); /*disable VE pll*/ aw_writel(aw_readl(SW_CCM_CORE_VE_PLL_REG)&~(1<<15),SW_CCM_CORE_VE_PLL_REG); /*COREPLL to 24M*/ aw_writel((aw_readl(SW_CCM_AHB_APB_CFG_REG)&BUS_CCLK_MASK)|BUS_CCLK_24M,SW_CCM_AHB_APB_CFG_REG); standby_delay(100); /*down core power*/ #if EN_POWER_D standby_twi_init(0); twi_byte_rw(TWI_OP_RD,0x34,0x23,&data[0]); data[2] = 0x0C; // 1V twi_byte_rw(TWI_OP_WR,0x34,0x23,&data[2]); #endif /*COREPLL to 32K*/ aw_writel((aw_readl(SW_CCM_AHB_APB_CFG_REG)&BUS_CCLK_MASK)|BUS_CCLK_32K,SW_CCM_AHB_APB_CFG_REG); standby_delay(50); /*disable HOSC and LDO*/ aw_writel(aw_readl(SW_CCM_AUDIO_HOSC_PLL_REG)&~(1|(1<<15)),SW_CCM_AUDIO_HOSC_PLL_REG); #if MODIFY_AHB_APB_EN aw_writel((1<<13)|(1<<16)|(1),SW_CCM_AHB_GATE_REG); aw_writel((1<<5)|1,SW_CCM_APB_GATE_REG); #endif }
/* ********************************************************************************************************* * standby_power_init * * Description: init power for standby. * * Arguments : none; * * Returns : result; ********************************************************************************************************* */ __s32 standby_power_init(__u32 wakeup_src) { __u8 reg_val; standby_twi_init(AXP_IICBUS); if(wakeup_src & AXP_WAKEUP_KEY) { /* enable pek long/short */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN3, ®_val); reg_val |= 0x03; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN3, ®_val); } if(wakeup_src & AXP_WAKEUP_LONG_KEY) { /* enable pek long */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN3, ®_val); reg_val |= 0x01; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN3, ®_val); /*pek long period setting: 1s*/ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_PEK, ®_val); reg_val &= 0xcf; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_PEK, ®_val); } if(wakeup_src & AXP_WAKEUP_SHORT_KEY) { /* enable pek short */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN3, ®_val); reg_val |= 0x02; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN3, ®_val); } if(wakeup_src & AXP_WAKEUP_DESCEND) { /* enable pek desend trigger */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN5, ®_val); reg_val |= 0x20; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN5, ®_val); } if(wakeup_src & AXP_WAKEUP_ASCEND) { /* enable pek ascend trigger */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN5, ®_val); reg_val |= 0x40; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN5, ®_val); } if(wakeup_src & AXP_WAKEUP_LOWBATT) { /* enable low voltage warning */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN4, ®_val); reg_val |= 0x03; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN4, ®_val); /* clear pending */ reg_val |= 0x03; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQ4, ®_val); } if(wakeup_src & AXP_WAKEUP_USB) { /* enable usb plug-in / plug-out */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN1, ®_val); reg_val |= 0x03<<2; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN1, ®_val); } if(wakeup_src & AXP_WAKEUP_AC) { /* enable ac plug-in / plug-out */ twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN1, ®_val); reg_val |= 0x03<<5; twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN1, ®_val); } return 0; }