_start(void)
{
/*
* Depending on the config parameter, enable or disable the WDT.
*/
#if !defined(CONFIG_HW_WATCHDOG)
wdt_disable();
#else
wdt_enable();
#endif
/*
* Make sure interrupts are disabled.
*/
__disable_irq();
#ifdef CONFIG_LPC18XX_NORFLASH_BOOTSTRAP_WORKAROUND
/*
* Reload the whole U-Boot image from NOR flash.
* The Boot ROM on LPC4350 parts cannot load more than 32KBytes
* from NOR flash when booting.
*/
lpc18xx_bootstrap_from_norflash();
#endif /* CONFIG_LPC18XX_NORFLASH_BOOTSTRAP_WORKAROUND */
/*
* Copy data and initialize BSS
* This is in lieu of the U-boot "conventional" relocation
* of code & data from Flash to RAM.
* With Cortex-M3, we execute from NVRAM (internal Flash),
* having relocated data to internal RAM (and having cleared the BSS
* area in internal RAM as well)
* Stack grows downwards; the stack base is set-up by the first
* value in the first word in the vectors.
*/
memcpy(&_data_start, &_data_lma_start, &_data_end - &_data_start);
memset(&_bss_start, 0, &_bss_end - &_bss_start);
/*
* In U-boot (armboot) lingvo, "go to the C code" -
* in fact, with M3, we are at the C code from the very beginning.
* In actuality, this is the jump to the ARM generic start code.
* ...
* Note initialization of _armboot_start below. The ARM generic
* code expects that this variable is set to the upper boundary of
* the malloc pool area.
* For Cortex-M3, where we do not relocate the code to RAM, I set
* the malloc pool right behind the stack. See how armboot_start
* is defined in the CPU specific .lds file.
*/
_armboot_start = (unsigned long)&_mem_stack_base;
start_armboot();
}
_start(void)
{
/*
* Make sure interrupts are disabled.
*/
__disable_irq();
/*
* Depending on the config parameter, enable or disable the WDT.
*/
#if !defined(CONFIG_HW_WATCHDOG)
#if !defined(CONFIG_SYS_M2S)
wdt_disable();
#endif
#else
wdt_enable();
#endif
#ifdef CONFIG_LPC18XX_NORFLASH_BOOTSTRAP_WORKAROUND
/*
* Reload the whole U-Boot image from SPIFI.
* *** The Boot ROM on LPC4350 parts cannot load more than 32KBytes
* from NOR flash when booting.***
*
* Boot from SPIFI only
*/
// lpc18xx_bootstrap_from_spifi();
#endif /* CONFIG_LPC18XX_NORFLASH_BOOTSTRAP_WORKAROUND */
//
// Copy sections from Flash
//
unsigned int LoadAddr, ExeAddr, SectionLen, loop;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__section_table_start;
// Copy the text,image_top and data sections from flash to SRAM and RAM.
while (SectionTableAddr < &__section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
unsigned int *pulDest = (unsigned int*) ExeAddr;
unsigned int *pulSrc = (unsigned int*) LoadAddr;
for (loop = 0; loop < SectionLen; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
unsigned int *pulDest = (unsigned int*) &_bss_start;
for (loop = 0; loop < (&_bss_end - &_bss_start); loop = loop + 4)
*pulDest++ = 0;
/*
* In U-boot (armboot) lingvo, "go to the C code" -
* in fact, with M3, we are at the C code from the very beginning.
* In actuality, this is the jump to the ARM generic start code.
* ...
* Note initialization of _armboot_start below. The ARM generic
* code expects that this variable is set to the upper boundary of
* the malloc pool area.
* For Cortex-M3, where we do not relocate the code to RAM, I set
* the malloc pool right behind the stack. See how armboot_start
* is defined in the CPU specific .lds file.
*/
// Clear all pending interrupts in the NVIC
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
unsigned int irqpendloop;
for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
*(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF;
}
#ifdef CONFIG_LPC18XX_USB
// Reenable interrupts
__enable_irq();
#endif
// ******************************
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *)vectors!=(unsigned int *) 0x00000000) {
// CMSIS : SCB->VTOR = <address of vector table>
*pSCB_VTOR = (unsigned int)vectors;
}
_armboot_start = (unsigned long)&_mem_stack_base;
start_armboot();
}
