void io_init(void) { stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOA); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOB); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOC); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOD); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE); #if 0 /* JTAG TRST Pin */ stm32_gpio_mode(MODSW, INPUT, SPEED_LOW); #endif /* USART5 TX */ stm32_gpio_mode(UART5_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(UART5_TX, GPIO_AF8); /* USART5 RX */ stm32_gpio_mode(UART5_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(UART5_RX, GPIO_AF8); /* USART6_TX */ stm32_gpio_mode(UART6_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(UART6_TX, GPIO_AF7); /* USART6_RX */ stm32_gpio_mode(UART6_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(UART6_RX, GPIO_AF7); }
void isink_init(void) { struct stm32f_dac * dac = STM32_DAC; struct stm32f_tim * tim = STM32_TIM4; uint32_t div; stm32_gpio_clr(SINK1); stm32_gpio_clr(SINK2); stm32_gpio_clr(SINK3); stm32_gpio_clr(SINK4); stm32_gpio_mode(SINK1, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK4, OUTPUT, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_af(SINK1, GPIO_AF2); stm32_gpio_af(SINK2, GPIO_AF2); stm32_gpio_af(SINK3, GPIO_AF2); /* Timer clock enable */ stm32_clk_enable(STM32_RCC, STM32_CLK_TIM4); /* get the total divisior */ div = (stm32f_tim1_hz + (FREQ_1MHZ / 2)) / FREQ_1MHZ; /* Timer configuration */ tim->cr1 = 0; tim->psc = div - 1; tim->arr = 1; tim->ccmr1 = TIM_OC1M_PWM_MODE2 | TIM_OC2M_PWM_MODE2; tim->ccmr2 = TIM_OC3M_PWM_MODE2 | TIM_OC4M_PWM_MODE2; tim->ccer = TIM_CC1E | TIM_CC2E | TIM_CC3E | TIM_CC4E; // TIM_CC1P | TIM_CC2P | TIM_CC3P | TIM_CC4P; tim->ccr1 = 1; tim->ccr2 = 1; tim->ccr3 = 1; tim->ccr4 = 1; tim->dier = TIM_UIE; /* Update interrupt enable */ cm3_irq_pri_set(STM32_IRQ_TIM4, IRQ_PRIORITY_HIGH); /* Enable interrupt */ cm3_irq_enable(STM32_IRQ_TIM4); /* I/O pins config */ stm32_gpio_mode(IRATE, ANALOG, 0); stm32_gpio_clr(IRATE); /* DAC clock enable */ stm32_clk_enable(STM32_RCC, STM32_CLK_DAC); /* DAC disable */ dac->cr = 0; /* DAC configure */ dac->cr = DAC_EN2; /* DAC channel 2 initial value */ dac->dhr12r2 = 0; /* DAC channel 1 initial value */ dac->dhr12r1 = 0; isink_drv.mode = -1; }
/* ------------------------------------------------------------------------- * Test * ------------------------------------------------------------------------- */ void io_init(void) { thinkos_udelay_factor(&udelay_factor); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOA); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOB); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOC); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOD); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE); /* USART5 TX */ stm32_gpio_mode(UART5_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(UART5_TX, GPIO_AF8); /* USART5 RX */ stm32_gpio_mode(UART5_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(UART5_RX, GPIO_AF8); stm32_gpio_mode(IO_RS485_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(IO_RS485_RX, RS485_USART_AF); stm32_gpio_mode(IO_RS485_TX, ALT_FUNC, PUSH_PULL | SPEED_MED); stm32_gpio_af(IO_RS485_TX, RS485_USART_AF); stm32_gpio_mode(IO_RS485_MODE, OUTPUT, PUSH_PULL | SPEED_LOW); stm32_gpio_set(IO_RS485_MODE); /* USART6_TX */ stm32_gpio_mode(UART6_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(UART6_TX, GPIO_AF7); /* USART6_RX */ stm32_gpio_mode(UART6_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(UART6_RX, GPIO_AF7); }
/* * Initialize IO pins and SPI low level device */ static int lattice_ice40_io_init(unsigned int freq) { struct stm32f_spi * spi = STM32F_SPI3; unsigned int div; int br; /* Enable peripheral clock */ stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOB); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOC); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE); stm32_clk_enable(STM32_RCC, STM32_CLK_SPI3); /* Configure IO pins */ stm32_gpio_mode(ICE40_CDONE, INPUT, PULL_UP); stm32_gpio_set(ICE40_CRESET); stm32_gpio_mode(ICE40_CRESET, OUTPUT, SPEED_MED); stm32_gpio_set(ICE40_SPI_SS); stm32_gpio_mode(ICE40_SPI_SS, OUTPUT, SPEED_MED); stm32_gpio_mode(ICE40_SPI_SCK, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(ICE40_SPI_SCK, GPIO_AF6); stm32_gpio_mode(ICE40_SPI_SDO, ALT_FUNC, PULL_UP); stm32_gpio_af(ICE40_SPI_SDO, GPIO_AF6); stm32_gpio_mode(ICE40_SPI_SDI, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(ICE40_SPI_SDI, GPIO_AF6); /* Configure SPI */ div = stm32_clk_hz(STM32_CLK_SPI3) / freq / 2; br = 31 - __clz(div); if (div > (1 << br)) br++; DCC_LOG3(LOG_TRACE, "SPI freq=%d div=%d br=%d", freq, div, br); spi->cr1 = 0; spi->cr2 = 0; spi->i2scfgr = 0; spi->i2spr = 0; /* Master mode, MSB first */ spi->cr1 = SPI_SPE | SPI_BR_SET(br) | SPI_MSTR | SPI_SSM | SPI_SSI; return 0; }
void periodic_timer_init(uint32_t freq) { struct stm32f_tim * tim = STM32F_TIM3; uint32_t div; uint32_t pre; uint32_t n; /* get the total divisior */ div = ((stm32f_tim1_hz) + (freq / 2)) / freq; /* get the minimum pre scaler */ pre = (div / 65536) + 1; /* get the reload register value */ n = (div + pre / 2) / pre; /* Timer clock enable */ stm32_clk_enable(STM32_RCC, STM32_CLK_TIM3); /* Timer configuration */ tim->psc = pre - 1; tim->arr = n - 1; tim->cnt = n - 1; tim->cr1 = TIM_CEN; /* Enable counter */ tim->egr = TIM_UG; /* Force an update */ while (tim->sr == 0); tim->sr = 0; tim->dier = TIM_UIE; /* Update interrupt enable */ /* enable interrupts */ cm3_irq_enable(STM32F_IRQ_TIM3); }
void stm32f_fsmc_init(void) { struct stm32f_fsmc * fsmc = STM32F_FSMC; DCC_LOG(LOG_TRACE, "."); /* Flexible static memory controller module clock enable */ stm32_clk_enable(STM32_RCC, STM32_CLK_FSMC); #if 0 int i; /* Configure IO pins */ stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOD); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE); for (i = 0; i < sizeof(fsmc_io) / sizeof(gpio_io_t); i++) { gpio_io_t io = fsmc_io[i]; stm32_gpio_mode(STM32_GPIO(io.port), io.pin, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_af(STM32_GPIO(io.port), io.pin, GPIO_AF12); } stm32_gpio_mode(STM32_GPIO(GPIOD), 6, INPUT, PUSH_PULL | SPEED_HIGH); #endif fsmc->bcr1 = FSMC_CBURSTRW | FSMC_WREN | FSMC_BURSTEN | FSMC_MWID_16 | FSMC_MTYP_PSRAM | FSMC_MUXEN | /* Address/Data multiplexed */ FSMC_MBKEN | FSMC_WAITEN | FSMC_WAITPOL; fsmc->btr1 = FSMC_ACCMOD_A | FSMC_DATLAT_SET(0) | FSMC_CLKDIV_SET(3) | FSMC_BUSTURN_SET(0) | FSMC_DATAST_SET(0) | FSMC_ADDHDL_SET(0) | FSMC_ADDSET_SET(0); fsmc->bwtr1 = FSMC_ACCMOD_A | FSMC_DATLAT_SET(0) | FSMC_CLKDIV_SET(1) | FSMC_BUSTURN_SET(0) | FSMC_DATAST_SET(0) | FSMC_ADDHDL_SET(0) | FSMC_ADDSET_SET(0); }
static void trdp_rand_init(void) { struct stm32_rng * rng = STM32_RNG; /* Enable RNG clock */ stm32_clk_enable(STM32_RCC, STM32_CLK_RNG); /* Enable the random number generator */ rng->cr = RNG_RNGEN; }
void capture_init(void) { struct capture_drv * drv = &uart2_capture_drv; struct stm32_usart * uart = STM32_USART2; uint32_t clk; DCC_LOG2(LOG_TRACE, "drv=%p uart=%p...", drv, uart); clk = profclk_get(); drv->rx_fifo.head = drv->rx_fifo.tail = 0; drv->rx_fifo.seq = 0; drv->rx_fifo.buf[0].clk = clk; drv->rx_fifo.buf[0].cnt = 0; drv->rx_fifo.buf[0].seq = 0; drv->rx_fifo.clk = clk; #if SERIAL_STATS_ENABLE drv->err_cnt = 0; drv->ore_cnt = 0; drv->fe_cnt = 0; #endif drv->idle_bits = 2; /* clock enable */ stm32_clk_enable(STM32_RCC, STM32_CLK_USART2); /* UART --------------------------------------------------------------- */ /* Disable UART */ uart->cr1 = 0; /* Clear pending TC and BRK interrupts */ uart->sr = 0; uart->gtpr = 1; capture_baudrate_set(SERIAL_BAUDRATE); /* configure the UART */ uart->cr3 = USART_ONEBIT; /* Configure 8N1 */ uart->cr2 = USART_STOP_1; /* enable UART, RX and IDLE interrupts */ uart->cr1 = USART_UE | USART_RXNEIE; /* Errors interrupt */ uart->cr3 |= USART_EIE; /* configure interrupts */ cm3_irq_pri_set(STM32_IRQ_USART2, IRQ_PRIORITY_HIGHEST); /* enable interrupts */ cm3_irq_enable(STM32_IRQ_USART2); }
void oneshot_timer_init(uint32_t freq) { struct stm32f_tim * tim = STM32F_TIM4; unsigned int div; /* Timer clock enable */ stm32_clk_enable(STM32_RCC, STM32_CLK_TIM4); /* get the total divisior */ div = (stm32f_tim2_hz + (freq / 2)) / freq; DCC_LOG1(LOG_TRACE, "div=%d", div); /* Timer configuration */ tim->psc = div - 1; tim->arr = 0; tim->cnt = 0; tim->dier = TIM_UIE; /* Update interrupt enable */ tim->cr1 = TIM_CMS_EDGE | TIM_OPM | TIM_URS; cm3_irq_enable(STM32F_IRQ_TIM4); }
struct serdrv * serdrv_init(unsigned int speed) { struct serdrv * drv = &serial2_dev; struct stm32_usart * uart = STM32_USART2; DCC_LOG1(LOG_MSG, "speed=%d", speed); drv->tx_fifo.head = drv->tx_fifo.tail = 0; drv->rx_fifo.head = drv->rx_fifo.tail = 0; drv->txie = CM3_BITBAND_DEV(&uart->cr1, 7); thinkos_flag_give(SERDRV_TX_FLAG); /* clock enable */ stm32_clk_enable(STM32_RCC, STM32_CLK_USART2); /********************************************* * USART *********************************************/ stm32_usart_init(uart); stm32_usart_baudrate_set(uart, speed); stm32_usart_mode_set(uart, SERIAL_8N1); /* Enable DMA for transmission and reception */ // uart->cr3 |= USART_DMAT | USART_DMAR; /* enable idle line interrupt */ /* enable RX interrupt */ uart->cr1 |= USART_RXNEIE | USART_IDLEIE; /* enable UART */ stm32_usart_enable(uart); /* configure interrupts */ cm3_irq_pri_set(STM32_IRQ_USART2, IRQ_PRIORITY_LOW); /* enable interrupts */ cm3_irq_enable(STM32_IRQ_USART2); return drv; }
void rs485_init(struct rs485_link * lnk, struct stm32_usart * uart, unsigned int speed, struct stm32f_dma * dma, int dma_chan_id, int rx_dma_strm_id, int tx_dma_strm_id) { struct stm32f_dma_stream * tx_dma_strm; struct stm32f_dma_stream * rx_dma_strm; uint32_t us; int c; tracef("%s():...", __func__); lnk->uart = uart; lnk->dma = dma; lnk->tx.pend_pkt = NULL; lnk->uart_irq = stm32_usart_irq_lookup(uart); DCC_LOG1(LOG_TRACE, "UART IRQ %d", lnk->uart_irq); /* DMA clock enable */ if (dma == STM32F_DMA1) { stm32_clk_enable(STM32_RCC, STM32_CLK_DMA1); lnk->tx.dma_irq = stm32f_dma1_irqnum_lut[tx_dma_strm_id]; lnk->rx.dma_irq = stm32f_dma1_irqnum_lut[rx_dma_strm_id]; DCC_LOG3(LOG_TRACE, "DMA1: chan=%d tx_irq=%d rx_irq=%d", dma_chan_id, lnk->tx.dma_irq, lnk->rx.dma_irq); } else { stm32_clk_enable(STM32_RCC, STM32_CLK_DMA2); lnk->tx.dma_irq = stm32f_dma2_irqnum_lut[tx_dma_strm_id]; lnk->rx.dma_irq = stm32f_dma2_irqnum_lut[rx_dma_strm_id]; DCC_LOG3(LOG_TRACE, "DMA2: chan=%d tx_irq=%d rx_irq=%d", dma_chan_id, lnk->tx.dma_irq, lnk->rx.dma_irq); } /* TX DMA */ lnk->tx.dma_id = tx_dma_strm_id; lnk->tx.isr = dma_isr_bitband(dma, tx_dma_strm_id); lnk->tx.ifcr = dma_ifcr_bitband(dma, tx_dma_strm_id); DCC_LOG2(LOG_TRACE, "isr=0x%p ifcr=0x%p", lnk->tx.isr, lnk->tx.ifcr); tx_dma_strm = &dma->s[tx_dma_strm_id]; lnk->tx.dma_strm = tx_dma_strm; DCC_LOG2(LOG_TRACE, "TX DMA stream[%d]=0x%p", lnk->tx.dma_id, tx_dma_strm); /* Disable DMA stream */ tx_dma_strm->cr = 0; while (tx_dma_strm->cr & DMA_EN); /* Wait for the channel to be ready .. */ /* clear all interrupt flags */ lnk->tx.ifcr[FEIF_BIT] = 1; lnk->tx.ifcr[DMEIF_BIT] = 1; lnk->tx.ifcr[TEIF_BIT] = 1; lnk->tx.ifcr[HTIF_BIT] = 1; lnk->tx.ifcr[TCIF_BIT] = 1; /* configure TX DMA stream */ tx_dma_strm->cr = DMA_CHSEL_SET(dma_chan_id) | DMA_MBURST_1 | DMA_PBURST_1 | DMA_MSIZE_8 | DMA_PSIZE_8 | DMA_MINC | DMA_DIR_MTP | DMA_TCIE | DMA_TEIE; tx_dma_strm->par = &uart->dr; tx_dma_strm->fcr = DMA_FEIE | DMA_DMDIS | DMA_FTH_FULL; /* RX DMA */ lnk->rx.dma_id = rx_dma_strm_id; lnk->rx.isr = dma_isr_bitband(dma, rx_dma_strm_id); lnk->rx.ifcr = dma_ifcr_bitband(dma, rx_dma_strm_id); rx_dma_strm = &dma->s[rx_dma_strm_id]; lnk->rx.dma_strm = rx_dma_strm; DCC_LOG2(LOG_TRACE, "RX DMA stream[%d]=0x%p", lnk->rx.dma_id, rx_dma_strm); /* Disable DMA stream */ rx_dma_strm->cr = 0; while (rx_dma_strm->cr & DMA_EN); /* Wait for the channel to be ready .. */ /* clear all interrupt flags */ lnk->rx.ifcr[FEIF_BIT] = 1; lnk->rx.ifcr[DMEIF_BIT] = 1; lnk->rx.ifcr[TEIF_BIT] = 1; lnk->rx.ifcr[HTIF_BIT] = 1; lnk->rx.ifcr[TCIF_BIT] = 1; /* configure RX DMA stream */ rx_dma_strm->cr = DMA_CHSEL_SET(dma_chan_id) | DMA_MBURST_1 | DMA_PBURST_1 | DMA_MSIZE_8 | DMA_PSIZE_8 | DMA_MINC | DMA_DIR_PTM | DMA_TCIE | DMA_TEIE; rx_dma_strm->par = &uart->dr; rx_dma_strm->fcr = DMA_FEIE | DMA_DMDIS | DMA_FTH_FULL; stm32_usart_init(uart); stm32_usart_baudrate_set(uart, speed); stm32_usart_mode_set(uart, SERIAL_8N1); /* 3 characters IDLE time: - 1 char in the TX holding buffer - 1 char in the TX shift register - 1 idle char */ us = ((30 * 1000 * 1000) / speed) + 1; lnk->idle_tm = (us / 1000) + 1; tracef("idle_tm = %d.%03d", lnk->idle_tm, us % 1000); tracef("%s() lnk->uart_irq=%d", __func__, lnk->uart_irq); #if 0 /* Enable SCLK pin */ uart->cr2 |= USART_CLKEN; #endif /* Enable DMA for transmission and reception */ uart->cr3 |= USART_DMAT | USART_DMAR; /* enable idle line interrupt */ uart->cr1 |= USART_IDLEIE; /* clear pending data */ c = uart->dr; (void)c; c = uart->dr; (void)c; stm32_usart_enable(uart); }