void ARMProcess::execute(Process *previous)
{
ARMProcess *p = (ARMProcess *) previous;
switchCoreState( p ? &p->m_kernelStack : ZERO,
m_pageDirectory,
m_kernelStack );
}
void IntelProcess::execute(Process *previous)
{
IntelProcess *p = (IntelProcess *) previous;
// Reload Task State Register (with kernel stack for interrupts)
kernelTss.esp0 = m_kernelStackBase;
//ltr(KERNEL_TSS_SEL);
// Activate the memory context of this process
m_memoryContext->activate();
// Switch kernel stack (includes saved userspace registers)
switchCoreState( p ? &p->m_kernelStack : ZERO,
m_kernelStack );
}
void ARMProcess::execute(Process *previous)
{
ARMProcess *p = (ARMProcess *) previous;
// No need to assign the process kernel stack somewhere (compared to TSS.esp0 for Intel).
// ARM cores have banked registers for each ARM mode. Once the stack
// register is set in the current ARM mode (supervisor), it will be saved
// in the banked (copied) stack register. When user code interrupts, the
// banked register will be applied for the stack automatically.
// Activate the memory context of this process
m_memoryContext->activate();
switchCoreState( p ? &p->m_kernelStack : ZERO,
m_kernelStack );
}
