kfree(mpe42_clk_a_switch_cfg);
mpe42_clk_a_switch_cfg = NULL;
pr_debug("stm pm mpe42: ClockGens A: restored\n");
}
#define MPE42_DDR_PLL_CFG MPE42_DDR_SYSCFG(7502)
#define MPE42_DDR_PLL_STATUS MPE42_DDR_SYSCFG(7569)
#define SELF_REFRESH_ON_PCTL 1
static const long stx_mpe42_ddr0_enter[] = {
#ifdef SELF_REFRESH_ON_PCTL
synopsys_ddr32_in_self_refresh(MPE42_DDR_PCTL_BASE(0)),
#else
UPDATE32(MPE42_DDR_PWR_DWN(0), ~MPE42_DDR_PWR_DWN_REQ, 0),
WHILE_NE32(MPE42_DDR_PWR_STATUS(0), MPE42_DDR_PWR_STATUS_ACK, 0),
#endif
synopsys_ddr32_phy_standby_enter(MPE42_DDR_PCTL_BASE(0)),
};
static const long stx_mpe42_ddr1_enter[] = {
#ifdef SELF_REFRESH_ON_PCTL
synopsys_ddr32_in_self_refresh(MPE42_DDR_PCTL_BASE(1)),
#else
UPDATE32(MPE42_DDR_PWR_DWN(1), ~MPE42_DDR_PWR_DWN_REQ, 0),
WHILE_NE32(MPE42_DDR_PWR_STATUS(1), MPE42_DDR_PWR_STATUS_ACK, 0),
#define SASC_SWITCH_CFG(x) (0x1c + (x) * 0x4)
#define CLK_A1_BASE 0xFEA20000
#define DDR_CLK_ID 5
#define DDR_CLK_SHIFT (DDR_CLK_ID * 2)
#define SYSCONF_CPU_722 (STIG125_SYSCONF_CPU_BASE + 0x58)
#define SYSCONF_CPU_760 (STIG125_SYSCONF_CPU_BASE + 0xf0)
static void __iomem *clks_base[2];
static struct stm_wakeup_devices stig125_wkd;
static long stig125_ddr0_enter[] = {
synopsys_ddr32_in_self_refresh(STIG125_DDR_PCTL_BASE),
synopsys_ddr32_phy_standby_enter(STIG125_DDR_PCTL_BASE),
POKE32(CLK_A1_BASE + SASC_SWITCH_CFG(0), 0),
POKE32(CLK_A1_BASE + SASC_POWER_CFG, 0x3),
/* bypass and disable the A9.PLL */
OR32(SYSCONF_CPU_722, 1 << 2),
OR32(SYSCONF_CPU_722, 1),
END_MARKER,
};
static long stig125_ddr0_exit[] = {
/* enable, wait and don't bypass the A9.PLL */
#include <linux/stm/mpe41-periphs.h>
#include <linux/stm/sysconf.h>
#include <linux/stm/clk.h>
#include <linux/stm/wakeup_devices.h>
#include "../suspend.h"
#include <mach/hardware.h>
#include <mach/mpe41.h>
#include <mach/soc-fli7610.h>
#include <asm/hardware/gic.h> /* gic offset and struct gic_chip_data */
#include <linux/stm/poke_table.h>
#include <linux/stm/synopsys_dwc_ddr32.h>
static const long fli7610_ddr0_enter[] = {
synopsys_ddr32_in_self_refresh(MPE41_DDR0_PCTL_BASE),
synopsys_ddr32_phy_standby_enter(MPE41_DDR0_PCTL_BASE),
};
static const long fli7610_ddr1_enter[] = {
synopsys_ddr32_in_self_refresh(MPE41_DDR1_PCTL_BASE),
synopsys_ddr32_phy_standby_enter(MPE41_DDR1_PCTL_BASE),
};
static const long fli7610_ddr0_exit[] = {
synopsys_ddr32_phy_standby_exit(MPE41_DDR0_PCTL_BASE),
synopsys_ddr32_out_of_self_refresh(MPE41_DDR0_PCTL_BASE),
};
static const long fli7610_ddr1_exit[] = {
synopsys_ddr32_phy_standby_exit(MPE41_DDR1_PCTL_BASE),
/* *************************
* STANDBY INSTRUCTION TABLE
* *************************
*/
static unsigned long stxh205_standby_table[] __cacheline_aligned = {
END_MARKER,
END_MARKER
};
/* *********************
* MEM INSTRUCTION TABLE
* *********************
*/
static unsigned long stxh205_mem_table[] __cacheline_aligned = {
synopsys_ddr32_in_self_refresh(DDR3SS_REG),
synopsys_ddr32_phy_standby_enter(DDR3SS_REG),
OR32(CLK_A1_BASE + CKGA_POWER_CFG, 3),
/* END. */
END_MARKER,
/*
* Turn-on DDR clock:
* The DDR subsystem uses the channel coming from A1.HS_0
* this means there is _no_ ClockGen_D...
*
* - turn on the A1.PLLs
* - wait both the PLLs are locked
*/
UPDATE32(CLK_A1_BASE + CKGA_POWER_CFG, 0, ~0x3),
static void __iomem *cga;
/* *************************
* STANDBY INSTRUCTION TABLE
* *************************
*/
static unsigned long fli7510_standby_table[] __cacheline_aligned = {
END_MARKER,
END_MARKER
};
/* *********************
* MEM INSTRUCTION TABLE
* *********************
*/
static unsigned long fli7510_mem_table[] __cacheline_aligned = {
synopsys_ddr32_in_self_refresh(DDR0_BASE_REG),
#if 0
OR32(DDR0_BASE_REG + DDR_PHY_IOCRV1, 1),
OR32(DDR0_BASE_REG + DDR_PHY_DXCCR, 1),
#endif
synopsys_ddr32_in_self_refresh(DDR1_BASE_REG),
#if 0
OR32(DDR1_BASE_REG + DDR_PHY_IOCRV1, 1),
OR32(DDR1_BASE_REG + DDR_PHY_DXCCR, 1),
OR32(DDR0_BASE_REG + DDR_PHY_PIR, 1 << 7),
OR32(DDR1_BASE_REG + DDR_PHY_PIR, 1 << 7),
#endif
END_MARKER,