void wdbSuspendSystemHere
(
void (*callback)(),
int arg
)
{
u_int lockKey;
WDB_IU_REGS regSet;
lockKey = intLock();
#if CPU==SIMNT
sysClkDisable();
#endif
if (WDB_CTX_SAVE (®Set) == 0)
{
_sigCtxRtnValSet (®Set, 1);
wdbSuspendSystem (®Set, callback, arg);
}
#if CPU==SIMNT
sysClkEnable();
#endif
intUnlock (lockKey);
}
STATUS sysClkRateSet(int ticksPerSecond)
{
BOOL running = FALSE;
if (ticksPerSecond < SYS_CLK_RATE_MIN || ticksPerSecond > SYS_CLK_RATE_MAX)
return (ERROR);
tps = ticksPerSecond;
running = timerRunning;
if (running)
{
sysClkDisable ();
sysClkEnable ();
}
return (OK);
}
void deinitTimer() {
TimerNodePtr tmp_node;
TimerItemPtr tmp_item;
timer_debug("deinitTimer: ");
g_timer_switcher = 0;
waitSemaphore(g_timer_end_sem);
destroySemaphore(g_timer_end_sem);
sysClkDisable();
destroySemaphore(g_timer_tick_sem);
while (g_timer_chain != NULL) {
tmp_node = g_timer_chain;
g_timer_chain = tmp_node->next;
removeTimerNode(tmp_node);
}
g_timer_chain = NULL;
deinitCallbackInfo();
timer_loginfo("deinit g_timer_chain success");
}
STATUS sysClkRateSet
(
int ticksPerSecond /* number of clock interrupts per second */
)
{
/* return ERROR if rate is not supported */
if (ticksPerSecond < SYS_CLK_RATE_MIN || ticksPerSecond > SYS_CLK_RATE_MAX)
return (ERROR);
sysClkTicksPerSecond = ticksPerSecond;
if (sysClkRunning)
{
sysClkDisable ();
sysClkEnable ();
}
return (OK);
}
STATUS sysToMonitor
(
int startType /* passed to ROM to tell it how to boot */
)
{
#if 0
FUNCPTR pRom;
int i;
volatile UINT32 intrAck;
#ifdef _WRS_CONFIG_SMP
cpuset_t cpuList;
volatile int idx;
int srcCpuId;
/* if the current core is not core0, we won't run sysToMonitor directly */
if (vxCpuIndexGet() != 0)
{
/*
* 0xFEFEFEFE means that all other cores are indicated to shutdown
* by core 0
*/
if ((startType & 0xFFFFFFF0) != 0xFEFEFEF0)
{
/* If not directed here then tell CPU 0 to enter sysToMonitor */
vxIpiConnect (INT_LVL_MPCORE_RESET,
(IPI_HANDLER_FUNC) (sysToMonitor),
(void *) (0xFEF00000 | startType | \
(vxCpuIndexGet() << 16)));
vxIpiEnable (INT_LVL_MPCORE_RESET);
vxIpiEmit (INT_LVL_MPCORE_RESET, 1);
/* wait for a reset from core 0 */
while(1);
}
/*
* If this is not core0, it must be informed by core0 to reboot
* through IPI. Therefore, we must acknowkedge the IPI interrupt.
* The IPI(SGI) interrupt information can not be got from Interrupt
* Acknowledge Register, because ISR in interrupt controller driver
* has read(to clear) this register.
*/
srcCpuId = (startType & 0xF) << 10;
*(volatile UINT32 *)(PBXA9_GIC_CPU_END_INTR) =
INT_LVL_MPCORE_RESET | srcCpuId;
/* flush data cache */
cacheFlush((CACHE_TYPE)DATA_CACHE, (void *)0, (size_t)ENTIRE_CACHE);
cachePipeFlush();
mmuCortexA8ADisable(); /* disable the MMU, cache(s) and write-buffer */
/* Make sure we go back to the bootMonitor loop */
pRom = (FUNCPTR)(ROM_TEXT_ADRS + 4);
(*pRom)(0); /* jump to boot ROM */
}
#endif /* _WRS_CONFIG_SMP */
sysClkDisable();
intIFLock();
#ifdef _WRS_CONFIG_SMP
/* here is the core 0 */
if ((startType & 0xFFF0000) == 0xFEF00000)
{
/*
* core0 is informed by other core through IPI to reboot, so we must
* acknowledge the IPI(SGI) interrupt.
*/
srcCpuId = (startType & 0x000F0000) >> 16;
*(volatile UINT32 *)(PBXA9_GIC_CPU_END_INTR) =
INT_LVL_MPCORE_RESET + (srcCpuId << 10);
startType = (startType & 0xFFFF);
}
static int __wind_sys_clkdisable(struct task_struct *curr, struct pt_regs *regs)
{
sysClkDisable();
return 0;
}