void ETH1_init(u8_t *mac_addr) { outpw(REG_CLK_HCLKEN, inpw(REG_CLK_HCLKEN) | (1 << 17)); // EMAC1 clk outpw(REG_CLK_DIVCTL8, (inpw(REG_CLK_DIVCTL8) & ~0xFF) | 0xA0); // MDC clk divider // Multi function pin setting outpw(REG_SYS_GPE_MFPL, (inpw(REG_SYS_GPE_MFPL) & ~0xFFFFFF00) | 0x11111100); outpw(REG_SYS_GPE_MFPH, (inpw(REG_SYS_GPE_MFPH) & ~0xFFFF) | 0x1111); // Reset MAC outpw(REG_EMAC1_MCMDR, 0x1000000); init_tx_desc(); init_rx_desc(); set_mac_addr(mac_addr); // need to reconfigure hardware address 'cos we just RESET emc... reset_phy(); outpw(REG_EMAC1_MCMDR, inpw(REG_EMAC1_MCMDR) | 0x121); // strip CRC, TX on, Rx on outpw(REG_EMAC1_MIEN, inpw(REG_EMAC1_MIEN) | 0x01250C11); // Except tx/rx ok, enable rdu, txabt, tx/rx bus error. sysInstallISR(IRQ_LEVEL_1, EMC1_TX_IRQn, (PVOID)ETH1_TX_IRQHandler); sysInstallISR(IRQ_LEVEL_1, EMC1_RX_IRQn, (PVOID)ETH1_RX_IRQHandler); sysEnableInterrupt(EMC1_TX_IRQn); sysEnableInterrupt(EMC1_RX_IRQn); ETH1_TRIGGER_RX(); sysSetTimerEvent(TIMER0, 200, (PVOID)chk_link); // check link status every 2 sec }
void i2cEnableInterrupt (BOOL bIsEnableINT) { UINT32 regdata; //k09144-1 sysSetInterruptType(IRQ_FI2C, LOW_LEVEL_SENSITIVE); //k08184-1 #ifdef ECOS if (bIsEnableINT) // enable I2C interrupt { cyg_interrupt_create(IRQ_FI2C, 1, 0, Int_Handler_FastI2C, NULL, &int_handle_I2C, &int_holder_I2C); cyg_interrupt_attach(int_handle_I2C); cyg_interrupt_unmask(IRQ_FI2C); } else { cyg_interrupt_mask(IRQ_FI2C); cyg_interrupt_detach(int_handle_I2C); } #else sysInstallISR(IRQ_LEVEL_1, IRQ_FI2C, (PVOID)Int_Handler_FastI2C); //IRQ_FI2C=24 if (bIsEnableINT) sysEnableInterrupt(IRQ_FI2C); //k03224-1 else sysDisableInterrupt (IRQ_FI2C); #endif _i2c_bINT_EN=bIsEnableINT; //k07195-1 //enable sensor I2C engine's interrupt if (bIsEnableINT) { regdata=inpw (REG_FastSerialBusCR)|0x02; outpw (REG_FastSerialBusCR,regdata); } //To clear interrupt status regdata=inpw (REG_FastSerialBusStatus)|0x03; outpw (REG_FastSerialBusStatus,regdata); /* enable I2C interrupt */ //k08204-1 sysEnableInterrupt(IRQ_FI2C); //k03224-1 }
/** * @brief Initialize spi interface and install interrupt callback function * @return always 0. * @retval 0 Success. */ int32_t spiInit(int32_t fd) { if(fd == 0) { sysInstallISR(IRQ_LEVEL_1, SPI0_IRQn, (PVOID)spi0ISR); sysEnableInterrupt(SPI0_IRQn); memset((void *)&spi_device[0], 0, sizeof(spi_dev)); } else { sysInstallISR(IRQ_LEVEL_1, SPI1_IRQn, (PVOID)spi1ISR); sysEnableInterrupt(SPI1_IRQn); memset((void *)&spi_device[1], 0, sizeof(spi_dev)); } sysSetLocalInterrupt(ENABLE_IRQ); return(0); }
/** * @brief Install ISR. * @param[in] fd is interface number. * @return always 0. * @retval 0 Success. */ int32_t i2cInit(int32_t fd) { if(fd == 0) { sysInstallISR(IRQ_LEVEL_1, I2C0_IRQn, (PVOID)i2c0ISR); sysEnableInterrupt(I2C0_IRQn); memset((void *)&i2c_device[0], 0, sizeof(i2c_dev)); } else { sysInstallISR(IRQ_LEVEL_1, I2C1_IRQn, (PVOID)i2c1ISR); sysEnableInterrupt(I2C1_IRQn); memset((void *)&i2c_device[1], 0, sizeof(i2c_dev)); } sysSetLocalInterrupt(ENABLE_IRQ); return(0); }
void vjpegInit(void) { #ifndef ECOS tt_rmutex_init(&g_vpJPEG.mtLock); tt_rmutex_init(&g_vpJPEG.mtLockEncoder); tt_rmutex_init(&g_vpJPEG.mtLockDecoder); tt_sem_init(&g_vpJPEG.semEncoder, 1); tt_sem_init(&g_vpJPEG.semDecoder, 1); tt_sem_down(&g_vpJPEG.semEncoder); tt_sem_down(&g_vpJPEG.semDecoder); #else cyg_mutex_init(&g_vpJPEG.mtLock); cyg_mutex_init(&g_vpJPEG.mtLockEncoder); cyg_mutex_init(&g_vpJPEG.mtLockDecoder); cyg_semaphore_init(&g_vpJPEG.semEncoder, 1); cyg_semaphore_init(&g_vpJPEG.semDecoder, 1); cyg_semaphore_wait(&g_vpJPEG.semEncoder); cyg_semaphore_wait(&g_vpJPEG.semDecoder); #endif g_vpJPEG.nRefCount = 0; g_vpJPEG.nRefCount_Encoder = 0; g_vpJPEG.nRefCount_Decoder = 0; g_vpJPEG.pJPEGEncodeBuffer = NULL; listInit (&g_vpJPEG.listEncodedJPEG); g_vpJPEG.nJPEGQua = 2; g_vpJPEG.bOnTheFly = TRUE; g_vpJPEG.nOnTheFlyCount = 0; #ifndef ECOS sysInstallISR(IRQ_LEVEL_1, IRQ_JPEG, (void*)jpegIntHandler); #else cyg_interrupt_disable(); cyg_interrupt_create(IRQ_JPEG, IRQ_LEVEL_1, NULL, &jpegIntHandler, &jpegIntHandler_DSR, &(g_vpJPEG.cygIntrHandle), &(g_vpJPEG.cygIntrBuffer)); cyg_interrupt_attach(g_vpJPEG.cygIntrHandle); cyg_interrupt_unmask(IRQ_JPEG); cyg_interrupt_enable(); #endif jpegSetIRQHandler(C_JPEG_CALLBACK_ENCODE_COMPLETE_INTERRUPT, vjpegEncoderCom_Callback); jpegSetIRQHandler(C_JPEG_CALLBACK_DECODE_COMPLETE_INTERRUPT, vjpegDecoderCom_Callback); jpegSetIRQHandler(C_JPEG_CALLBACK_DECODE_ERROR_INTERRUPT, vjpegDecoderErr_Callback); if(g_vpJPEG.bOnTheFly == TRUE) { jpegSetIRQHandler(C_JPEG_CALLBACK_ENCODE_SWONTHEFLY_WAIT_INTERRUPT, vjpegOnTheFlyCom_Callback); } bJPEGInit = TRUE; }
void capInit(BOOL bCapEngEnable, BOOL bCapIntEnable) #endif { int j; int i=sizeof(VCEInit)/sizeof(T_REG_INFO); for (j=0; j<i ;j++) outpw((CAP_BA+VCEInit[j].uAddr),VCEInit[j].uValue); if(bCapEngEnable==TRUE) { outpw(REG_CAPEngine,inpw(REG_CAPEngine)|0x01); } else { outpw(REG_CAPEngine,inpw(REG_CAPEngine)&0xfffffffe); } if(bCapIntEnable==TRUE) { #ifdef ECOS cyg_interrupt_disable(); cyg_interrupt_create(IRQ_VCE, 1, 0, capIntHandler, capIntHandlerDSR, &(t_eCos->cap_int_handle), &(t_eCos->cap_int)); cyg_interrupt_attach(t_eCos->cap_int_handle); cyg_interrupt_unmask(IRQ_VCE); cyg_interrupt_enable(); #else sysInstallISR(IRQ_LEVEL_1, IRQ_VCE, (PVOID)capIntHandler); // sysEnableInterrupt(IRQ_VCE); #endif outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x2); } else { #ifdef ECOS cyg_interrupt_mask(IRQ_VCE); cyg_interrupt_detach(t_eCos->cap_int_handle); cyg_interrupt_delete(t_eCos->cap_int_handle); #else sysDisableInterrupt(IRQ_VCE); #endif outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffffffd); } }
/*---------------------------------------------------------------------------------------------------------*/ int32_t main (void) { sysInitializeUART(); sysprintf("\n"); sysprintf("=========================\n"); sysprintf(" NUC970 USB VCOM \n"); sysprintf("=========================\n"); sysDisableCache(); sysInvalidCache(); sysSetMMUMappingMethod(MMU_DIRECT_MAPPING); sysEnableCache(CACHE_WRITE_BACK); sysInstallISR(HIGH_LEVEL_SENSITIVE|IRQ_LEVEL_1, USBD_IRQn, (PVOID)USBD_IRQHandler); /* enable CPSR I bit */ sysSetLocalInterrupt(ENABLE_IRQ); USBD_Open(&gsInfo, VCOM_ClassRequest, NULL); /* Endpoint configuration */ VCOM_Init(); sysEnableInterrupt(USBD_IRQn); /* Start transaction */ while(1) { if (USBD_IS_ATTACHED()) { USBD_Start(); break; } } while(1) { VCOM_TransferData(); } }
INT w5691StartPlay(AU_CB_FUNC_T *fnCallBack, INT nSamplingRate, INT nChannels, INT pcm_format) { UINT16 wTMV; UINT8 byTMB = 0; UINT8 byClockBase = 1; UINT8 eFormat = eSPEECH_FORMAT_SIGN_16BIT_PCM; INT nStatus; UINT8 byStartSpchCmd[8] = { 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 , 0x7f, 0x40 };//GFIFO start play command if (_W5691_Playing) return ERR_W5691_PLAY_ACTIVE; if (_W5691_Playing == 0) { memset((CHAR *)&_tW5691, 0, sizeof(_tW5691)); nStatus = w5691_init(); if (nStatus < 0) return nStatus; } #ifdef ECOS cyg_interrupt_disable(); sysSetInterruptType(GPIO_INT_NUM, LOW_LEVEL_SENSITIVE); cyg_interrupt_create(GPIO_INT_NUM, 1, 0, w5691_dma_isr, NULL, &_tW5691.int_handle_play, &_tW5691.int_holder_play); cyg_interrupt_attach(_tW5691.int_handle_play); cyg_interrupt_unmask(AU_PLAY_INT_NUM); cyg_interrupt_enable(); #else sysSetInterruptType(GPIO_INT_NUM, LOW_LEVEL_SENSITIVE); /* Install ISR */ sysInstallISR(IRQ_LEVEL_1, GPIO_INT_NUM, (PVOID)w5691_dma_isr); /* enable CPSR I bit */ sysSetLocalInterrupt(ENABLE_IRQ); /* Set AIC into SW mode */ // sysSetAIC2SWMode(); sysEnableInterrupt(GPIO_INT_NUM); #endif outpw(REG_GPIO_OE, inpw(REG_GPIO_OE) | (1<<USED_GPIO_NUM)); _tW5691.nPlaySamplingRate = nSamplingRate; _tW5691.fnPlayCallBack = fnCallBack; wTMV = (UINT16)(W5691_SYSTEM_CLOCK / _tW5691.nPlaySamplingRate) / byClockBase; while(wTMV > 511) { byClockBase <<= 1; wTMV >>= 1; byTMB++; } byStartSpchCmd[2] = (UINT8)eFormat | eSPEECH_FCH_PFIFO ; byStartSpchCmd[3] = (UINT8)(wTMV & 0xFF); byStartSpchCmd[4] = (UINT8)(wTMV >> 8); byStartSpchCmd[5] = byTMB; /* call back to fill DMA buffer*/ _tW5691.bPlayLastBlock = _tW5691.fnPlayCallBack((UINT8 *)_uAuPlayBuffAddr, Play_FIFO_Trigger_Length*2); /* send PCM data to w5691*/ ComDrv_SendCommandWithData(eCOMMAND_SEND_SPEECH_DATA, (UINT8 *)_uAuPlayBuffAddr, Play_FIFO_Trigger_Length*2); ComDrv_SendCommand(eCOMMAND_ENABLE_SPEECH_INTERRUPT); #ifdef SOFT_MODE ComDrv_SendFIFOData(CMD_COM_ID_GEN_FIFO,byStartSpchCmd,6); #else outpw(REG_ACTL_M80SIZE, 6+1); outpw(REG_ACTL_M80DATA0, 0x55 | byStartSpchCmd[0]<<8 | (byStartSpchCmd[1]<<16) | (byStartSpchCmd[2]<<24) ); outpw(REG_ACTL_M80DATA1, byStartSpchCmd[3] | (byStartSpchCmd[4]<<8) | (byStartSpchCmd[5]<<16)); outpw(REG_ACTL_M80ADDR, CMD_COM_ID_GEN_FIFO); outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) | W_GFIFO | W_IF12_ACT); while((inpw(REG_ACTL_M80CON)&W_IF12_ACT) != 0); outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) & ~W_GFIFO ); ComDrv_SendSimpleCommand(CMD_COM_ID_WAKE_UP,WAKE_UP_REG_INT); #endif Delay(0x5000); ComDrv_SetInterruptMask(1); #ifdef SOFT_MODE soft_read_status_flag_reg(); #else ComDrv_DisableInterrupt(); #endif ComDrv_EnableInterrupt(); _W5691_Playing=1; return 0; }