void pwm_io_config(enum PWM_CH ch) { if(ch == PWM_CH0) { syscon_SetPMCR1WithMask(QN_SYSCON,P27_MASK_PIN_CTRL, P27_PWM0_PIN_CTRL);//P2.7 pwm0 gpio_pull_set(GPIO_P27, GPIO_PULL_UP); } else if(ch == PWM_CH1) { syscon_SetPMCR1WithMask(QN_SYSCON,P26_MASK_PIN_CTRL, P26_PWM1_PIN_CTRL);//P2.6 pwm1 gpio_pull_set(GPIO_P26, GPIO_PULL_UP); } }
/** **************************************************************************************** * @brief Enable hardware flow control * @param[in] UART QN_UART0 or QN_UART1 * @description * Enable specified UART port hardware flow control ***************************************************************************************** */ void uart_flow_on(QN_UART_TypeDef *UART) { //uart_uart_SetCRWithMask(UART, UART_MASK_CTS_EN|UART_MASK_RTS_EN, MASK_ENABLE); #if CONFIG_ENABLE_DRIVER_UART0==TRUE // Switch RTS/CTS back if(UART == QN_UART0) { syscon_SetPMCR0WithMask(QN_SYSCON, P02_MASK_PIN_CTRL | P01_MASK_PIN_CTRL, P02_UART0_RTS_PIN_CTRL | P01_UART0_CTS_PIN_CTRL); } #endif #if CONFIG_ENABLE_DRIVER_UART1==TRUE if(UART == QN_UART1) { // NOTE!!!!! // Assume UART1 used P2.2 and P3.6 as RTS/CTS. Other case this snippet should be modified. syscon_SetPMCR1WithMask(QN_SYSCON, P22_MASK_PIN_CTRL | P36_MASK_PIN_CTRL, P22_UART1_RTS_PIN_CTRL | P36_UART1_CTS_PIN_CTRL); } #endif }
void pwm_io_config(void) { uint32_t reg; uint32_t reg_mask; /** * PMCR0 register pin configure */ reg = P07_SW_CLK_PIN_CTRL | P06_SW_DAT_PIN_CTRL; reg_mask = P07_MASK_PIN_CTRL | P06_MASK_PIN_CTRL; syscon_SetPMCR0WithMask(QN_SYSCON, reg_mask, reg); /** * PMCR1 register pin configure */ reg = P27_PWM0_PIN_CTRL | P26_PWM1_PIN_CTRL; reg_mask = P27_MASK_PIN_CTRL | P26_MASK_PIN_CTRL; syscon_SetPMCR1WithMask(QN_SYSCON, reg_mask, reg); // pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved ) syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA); syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA); }
/** **************************************************************************************** * @brief Disable hardware flow control * @param[in] UART QN_UART0 or QN_UART1 * @return TRUE * @description * Disable specified UART port hardware flow control ***************************************************************************************** */ bool uart_flow_off(QN_UART_TypeDef *UART) { //uart_uart_SetCRWithMask(UART, UART_MASK_CTS_EN|UART_MASK_RTS_EN, MASK_DISABLE); //return true; bool rt = false; uint32_t int_restore = 0; // Disable UART interrupt #if CONFIG_ENABLE_DRIVER_UART0==TRUE if(UART == QN_UART0) int_restore = NVIC->ISER[0] & ((1<<UART0_TX_IRQn) | (1<<UART0_RX_IRQn)); #endif #if CONFIG_ENABLE_DRIVER_UART1==TRUE if(UART == QN_UART1) int_restore = NVIC->ISER[0] & ((1<<UART1_TX_IRQn) | (1<<UART1_RX_IRQn)); #endif NVIC->ICER[0] = int_restore; do { // Check if no tx is ongoing if(UART_TX_FREE == uart_check_tx_free(UART)) break; // Disable rx (RTS/CTS -> GPIO high) #if CONFIG_ENABLE_DRIVER_UART0==TRUE if(UART == QN_UART0) { syscon_SetPMCR0WithMask(QN_SYSCON, P02_MASK_PIN_CTRL | P01_MASK_PIN_CTRL, P02_GPIO_2_PIN_CTRL | P01_GPIO_1_PIN_CTRL); gpio_write_pin(GPIO_P02, GPIO_HIGH); gpio_write_pin(GPIO_P01, GPIO_HIGH); } #endif #if CONFIG_ENABLE_DRIVER_UART1==TRUE if(UART == QN_UART1) { // NOTE!!!!! // Assume UART1 used P2.2 and P3.6 as RTS/CTS. Other case this snippet should be modified. syscon_SetPMCR1WithMask(QN_SYSCON, P22_MASK_PIN_CTRL | P36_MASK_PIN_CTRL, P22_GPIO_18_PIN_CTRL | P36_GPIO_30_PIN_CTRL); gpio_write_pin(GPIO_P22, GPIO_HIGH); gpio_write_pin(GPIO_P36, GPIO_HIGH); } #endif // Wait for 1 bytes duration to guarantee host has not started a tx at this time. // Assume buadrate 115200 delay(100); // Check if data has been received during the waiting time if(uart_uart_GetIntFlag(UART) & UART_MASK_RX_IF) { // Switch RTS/CTS back #if CONFIG_ENABLE_DRIVER_UART0==TRUE if(UART == QN_UART0) { syscon_SetPMCR0WithMask(QN_SYSCON, P02_MASK_PIN_CTRL | P01_MASK_PIN_CTRL, P02_UART0_RTS_PIN_CTRL | P01_UART0_CTS_PIN_CTRL); } #endif #if CONFIG_ENABLE_DRIVER_UART1==TRUE if(UART == QN_UART1) { // NOTE!!!!! // Assume UART1 used P2.2 and P3.6 as RTS/CTS. Other case this snippet should be modified. syscon_SetPMCR1WithMask(QN_SYSCON, P22_MASK_PIN_CTRL | P36_MASK_PIN_CTRL, P22_UART1_RTS_PIN_CTRL | P36_UART1_CTS_PIN_CTRL); } #endif // failed. break; } // success. rt = true; } while(false); // Restore uart interrupt status NVIC->ISER[0] = int_restore; return rt; }
int ble_i2c( const uint8_t * const pcCommandString,uint8_t* pcWriteBuffer,uint32_t commpare_length) { const int8_t *pcom; uint32_t pxParameterStringLength; uint8_t len; uint8_t i2c_addr ; uint8_t i2c_reg ; uint8_t i2c_data; if(pcCommandString[commpare_length+1] == '=') { //i2c_addr pcom = at_get_parameter((const int8_t*)pcCommandString + commpare_length + 2, 1, &pxParameterStringLength); if(pxParameterStringLength > 0) { i2c_addr = at_HEXstringToNum((const uint8_t *)pcom, pxParameterStringLength); } else { goto pram_err; } //i2c_reg pcom = at_get_parameter((const int8_t*)pcCommandString + commpare_length + 2, 2, &pxParameterStringLength); if(pxParameterStringLength > 0) { i2c_reg = at_HEXstringToNum((const uint8_t *)pcom, pxParameterStringLength); } else { goto pram_err; } // i2c R&W? pcom = at_get_parameter((const int8_t*)pcCommandString + commpare_length + 2, 0, &pxParameterStringLength); if(pxParameterStringLength == 1) { syscon_SetPMCR1WithMask(QN_SYSCON,P23_MASK_PIN_CTRL | P24_MASK_PIN_CTRL,P23_I2C_SDA_PIN_CTRL | P24_I2C_SCL_PIN_CTRL); i2c_init(I2C_SCL_RATIO(100000), i2c_buff, 4); if(pcom[0] == 'R') { i2c_data = I2C_BYTE_READ(i2c_addr,i2c_reg); if(i2c_is_finish()) { len = commpare_length+1; memcpy(pcWriteBuffer, pcCommandString, len); len += sprintf((char *)pcWriteBuffer + len,":0x%02x\r\nOK\r\n",i2c_data); return len; } goto pram_err; } else if(pcom[0] == 'W') { //i2c_data pcom = at_get_parameter((const int8_t*)pcCommandString + commpare_length + 2, 3, &pxParameterStringLength); if(pxParameterStringLength > 0) { i2c_data = at_HEXstringToNum((const uint8_t *)pcom, pxParameterStringLength); } else { goto pram_err; } I2C_BYTE_WRITE(i2c_addr, i2c_reg, i2c_data); if(!i2c_is_finish()) { goto pram_err; } } } else { goto pram_err; } } else { goto pram_err; } return sprintf((char*)pcWriteBuffer,"OK\r\n"); pram_err: return sprintf((char*)pcWriteBuffer,"ERR\r\n"); }