/* SOC initialization before the console is enabled. */
void car_soc_pre_console_init(void)
{
/* System Agent Early Initialization */
systemagent_early_init();
if (IS_ENABLED(CONFIG_UART_DEBUG))
pch_uart_init();
}
/* SOC initialization before the console is enabled */
void soc_pre_console_init(struct romstage_params *params)
{
/* System Agent Early Initialization */
systemagent_early_init();
if (IS_ENABLED(CONFIG_CONSOLE_UART8250MEM_32))
pch_uart_init();
}
asmlinkage void car_stage_entry(void)
{
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
struct chipset_power_state *ps = pmc_get_power_state();
console_init();
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
/* initialize Heci interface */
heci_init(HECI1_BASE_ADDRESS);
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);
pmc_set_disb();
if (!s3wake)
save_dimm_info();
if (postcar_frame_init(&pcf, 1 * KiB))
die("Unable to initialize postcar frame.\n");
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
* a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
run_postcar_phase(&pcf);
}
