/**
* Copies code to a working area. This will allocate room for the code plus the
* additional amount requested if the working area pointer is null.
*
* @param target Pointer to the target to copy code to
* @param code Pointer to the code area to be copied
* @param code_size Size of the code being copied
* @param additional Size of the additional area to be allocated in addition to
* code
* @param area Pointer to a pointer to a working area to copy code to
* @return Success or failure of the operation
*/
static int arm_code_to_working_area(struct target *target,
const uint32_t *code, unsigned code_size,
unsigned additional, struct working_area **area)
{
uint8_t code_buf[code_size];
int retval;
unsigned size = code_size + additional;
/* REVISIT this assumes size doesn't ever change.
* That's usually correct; but there are boards with
* both large and small page chips, where it won't be...
*/
/* make sure we have a working area */
if (NULL == *area) {
retval = target_alloc_working_area(target, size, area);
if (retval != ERROR_OK) {
LOG_DEBUG("%s: no %d byte buffer", __func__, (int) size);
return ERROR_NAND_NO_BUFFER;
}
}
/* buffer code in target endianness */
target_buffer_set_u32_array(target, code_buf, code_size / 4, code);
/* copy code to work area */
retval = target_write_memory(target, (*area)->address,
4, code_size / 4, code_buf);
return retval;
}
/** Checks whether a memory region is zeroed. */
int mips32_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *blank)
{
struct working_area *erase_check_algorithm;
struct reg_param reg_params[3];
struct mips32_algorithm mips32_info;
static const uint32_t erase_check_code[] = {
/* nbyte: */
0x80880000, /* lb $t0, ($a0) */
0x00C83024, /* and $a2, $a2, $t0 */
0x24A5FFFF, /* addiu $a1, $a1, -1 */
0x14A0FFFC, /* bne $a1, $zero, nbyte */
0x24840001, /* addiu $a0, $a0, 1 */
0x7000003F /* sdbbp */
};
/* make sure we have a working area */
if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
/* convert erase check code into a buffer in target endianness */
uint8_t erase_check_code_8[sizeof(erase_check_code)];
target_buffer_set_u32_array(target, erase_check_code_8,
ARRAY_SIZE(erase_check_code), erase_check_code);
target_write_buffer(target, erase_check_algorithm->address, sizeof(erase_check_code), erase_check_code_8);
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
init_reg_param(®_params[0], "r4", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, address);
init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
buf_set_u32(reg_params[1].value, 0, 32, count);
init_reg_param(®_params[2], "r6", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
int retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
erase_check_algorithm->address,
erase_check_algorithm->address + (sizeof(erase_check_code) - 4),
10000, &mips32_info);
if (retval == ERROR_OK)
*blank = buf_get_u32(reg_params[2].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
target_free_working_area(target, erase_check_algorithm);
return retval;
}
static int str9x_write_block(struct flash_bank *bank,
const uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
uint32_t buffer_size = 32768;
struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[4];
struct arm_algorithm arm_algo;
int retval = ERROR_OK;
/* see contib/loaders/flash/str9x.s for src */
static const uint32_t str9x_flash_write_code[] = {
/* write: */
0xe3c14003, /* bic r4, r1, #3 */
0xe3a03040, /* mov r3, #0x40 */
0xe1c430b0, /* strh r3, [r4, #0] */
0xe0d030b2, /* ldrh r3, [r0], #2 */
0xe0c130b2, /* strh r3, [r1], #2 */
0xe3a03070, /* mov r3, #0x70 */
0xe1c430b0, /* strh r3, [r4, #0] */
/* busy: */
0xe5d43000, /* ldrb r3, [r4, #0] */
0xe3130080, /* tst r3, #0x80 */
0x0afffffc, /* beq busy */
0xe3a05050, /* mov r5, #0x50 */
0xe1c450b0, /* strh r5, [r4, #0] */
0xe3a050ff, /* mov r5, #0xFF */
0xe1c450b0, /* strh r5, [r4, #0] */
0xe3130012, /* tst r3, #0x12 */
0x1a000001, /* bne exit */
0xe2522001, /* subs r2, r2, #1 */
0x1affffed, /* bne write */
/* exit: */
0xe1200070, /* bkpt #0 */
};
/* flash write code */
if (target_alloc_working_area(target, sizeof(str9x_flash_write_code),
&write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
uint8_t code[sizeof(str9x_flash_write_code)];
target_buffer_set_u32_array(target, code, ARRAY_SIZE(str9x_flash_write_code),
str9x_flash_write_code);
target_write_buffer(target, write_algorithm->address, sizeof(code), code);
/* memory buffer */
while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
if (buffer_size <= 256) {
/* we already allocated the writing code, but failed to get a
* buffer, free the algorithm */
target_free_working_area(target, write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
arm_algo.common_magic = ARM_COMMON_MAGIC;
arm_algo.core_mode = ARM_MODE_SVC;
arm_algo.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[3], "r3", 32, PARAM_IN);
while (count > 0) {
uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
target_write_buffer(target, source->address, thisrun_count * 2, buffer);
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
write_algorithm->address,
0, 10000, &arm_algo);
if (retval != ERROR_OK) {
LOG_ERROR("error executing str9x flash write algorithm");
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80) {
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
buffer += thisrun_count * 2;
address += thisrun_count * 2;
count -= thisrun_count;
}
target_free_working_area(target, source);
target_free_working_area(target, write_algorithm);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
return retval;
}
/* If this fn returns ERROR_TARGET_RESOURCE_NOT_AVAILABLE, then the caller can fall
* back to another mechanism that does not require onboard RAM
*
* Caller should not check for other return values specifically
*/
static int aduc702x_write_block(struct flash_bank *bank,
const uint8_t *buffer,
uint32_t offset,
uint32_t count)
{
struct target *target = bank->target;
uint32_t buffer_size = 7000;
struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[6];
struct arm_algorithm arm_algo;
int retval = ERROR_OK;
if (((count%2) != 0) || ((offset%2) != 0)) {
LOG_ERROR("write block must be multiple of two bytes in offset & length");
return ERROR_FAIL;
}
/* parameters:
r0 - address of source data (absolute)
r1 - number of halfwords to be copied
r2 - start address in flash (offset from beginning of flash memory)
r3 - exit code
r4 - base address of flash controller (0xFFFFF800)
registers:
r5 - scratch
r6 - set to 2, used to write flash command
*/
static const uint32_t aduc702x_flash_write_code[] = {
/* <_start>: */
0xe3a05008, /* mov r5, #8 ; 0x8 */
0xe5845004, /* str r5, [r4, #4] */
0xe3a06002, /* mov r6, #2 ; 0x2 */
/* <next>: */
0xe1c421b0, /* strh r2, [r4, #16] */
0xe0d050b2, /* ldrh r5, [r0], #2 */
0xe1c450bc, /* strh r5, [r4, #12] */
0xe5c46008, /* strb r6, [r4, #8] */
/* <wait_complete>: */
0xe1d430b0, /* ldrh r3, [r4] */
0xe3130004, /* tst r3, #4 ; 0x4 */
0x1afffffc, /* bne 1001c <wait_complete> */
0xe2822002, /* add r2, r2, #2 ; 0x2 */
0xe2511001, /* subs r1, r1, #1 ; 0x1 */
0x0a000001, /* beq 1003c <done> */
0xe3130001, /* tst r3, #1 ; 0x1 */
0x1afffff3, /* bne 1000c <next> */
/* <done>: */
0xeafffffe /* b 1003c <done> */
};
/* flash write code */
if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
&write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
uint8_t code[sizeof(aduc702x_flash_write_code)];
target_buffer_set_u32_array(target, code, ARRAY_SIZE(aduc702x_flash_write_code),
aduc702x_flash_write_code);
retval = target_write_buffer(target, write_algorithm->address, sizeof(code), code);
if (retval != ERROR_OK)
return retval;
/* memory buffer */
while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
if (buffer_size <= 256) {
/* we already allocated the writing code, but failed to get a buffer,
*free the algorithm */
target_free_working_area(target, write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
arm_algo.common_magic = ARM_COMMON_MAGIC;
arm_algo.core_mode = ARM_MODE_SVC;
arm_algo.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[3], "r3", 32, PARAM_IN);
init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
while (count > 0) {
uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
retval = target_write_buffer(target, source->address, thisrun_count, buffer);
if (retval != ERROR_OK)
break;
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, thisrun_count/2);
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);
retval = target_run_algorithm(target, 0, NULL, 5,
reg_params, write_algorithm->address,
write_algorithm->address +
sizeof(aduc702x_flash_write_code) - 4,
10000, &arm_algo);
if (retval != ERROR_OK) {
LOG_ERROR("error executing aduc702x flash write algorithm");
break;
}
if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1) {
/* FIX!!!! what does this mean??? replace w/sensible error message */
LOG_ERROR("aduc702x detected error writing flash");
retval = ERROR_FAIL;
break;
}
buffer += thisrun_count;
address += thisrun_count;
count -= thisrun_count;
}
target_free_working_area(target, source);
target_free_working_area(target, write_algorithm);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
destroy_reg_param(®_params[4]);
return retval;
}
static int ath79_spi_bitbang_chunk(struct flash_bank *bank,
uint8_t *data, int len, int *transferred)
{
struct target *target = bank->target;
struct ath79_flash_bank *ath79_info = bank->driver_priv;
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
int pracc_words;
/*
* These constants must match the worst case in the above code
* generator function ath79_spi_bitbang_codegen.
*/
const int pracc_pre_post = 26;
const int pracc_loop_byte = 8 * 2 + 2;
struct pracc_queue_info ctx = {
.ejtag_info = ejtag_info
};
int max_len = (PRACC_MAX_INSTRUCTIONS - pracc_pre_post) / pracc_loop_byte;
int to_xfer = len > max_len ? max_len : len;
int partial_xfer = len != to_xfer;
int padded_len = (to_xfer + 3) & ~3;
uint32_t *out = malloc(padded_len);
if (!out) {
LOG_ERROR("not enough memory");
return ERROR_FAIL;
}
*transferred = 0;
pracc_queue_init(&ctx);
LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08x, %p, %d)",
target, ath79_info->io_base, data, len);
LOG_DEBUG("max code %d => max len %d. to_xfer %d",
PRACC_MAX_INSTRUCTIONS, max_len, to_xfer);
pracc_words = ath79_spi_bitbang_codegen(
ath79_info, &ctx, data, to_xfer, partial_xfer);
LOG_DEBUG("Assembled %d instructions, %d stores",
ctx.code_count, ctx.store_count);
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, out, 1);
if (ctx.retval != ERROR_OK)
goto exit;
if (to_xfer & 3) { /* Not a multiple of 4 bytes. */
/*
* Need to realign last word since we didn't shift the
* full 32 bits.
*/
int missed_bytes = 4 - (to_xfer & 3);
out[pracc_words - 1] <<= BITS_PER_BYTE * missed_bytes;
}
/*
* pracc reads return uint32_t in host endianness, convert to
* target endianness.
* Since we know the ATH79 target is big endian and the SPI
* shift register has the bytes in highest to lowest bit order,
* this will ensure correct memory byte order regardless of host
* endianness.
*/
target_buffer_set_u32_array(target, (uint8_t *)out, pracc_words, out);
if (LOG_LEVEL_IS(LOG_LVL_DEBUG)) {
for (int i = 0; i < to_xfer; i++) {
LOG_DEBUG("bitbang %02x => %02x",
data[i], ((uint8_t *)out)[i]);
}
}
memcpy(data, out, to_xfer);
*transferred = to_xfer;
exit:
pracc_queue_free(&ctx);
free(out);
return ctx.retval;
}
static int str7x_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t buffer_size = 32768;
struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[6];
struct arm_algorithm arm_algo;
int retval = ERROR_OK;
/* see contib/loaders/flash/str7x.s for src */
static const uint32_t str7x_flash_write_code[] = {
/* write: */
0xe3a04201, /* mov r4, #0x10000000 */
0xe5824000, /* str r4, [r2, #0x0] */
0xe5821010, /* str r1, [r2, #0x10] */
0xe4904004, /* ldr r4, [r0], #4 */
0xe5824008, /* str r4, [r2, #0x8] */
0xe4904004, /* ldr r4, [r0], #4 */
0xe582400c, /* str r4, [r2, #0xc] */
0xe3a04209, /* mov r4, #0x90000000 */
0xe5824000, /* str r4, [r2, #0x0] */
/* busy: */
0xe5924000, /* ldr r4, [r2, #0x0] */
0xe1140005, /* tst r4, r5 */
0x1afffffc, /* bne busy */
0xe5924014, /* ldr r4, [r2, #0x14] */
0xe31400ff, /* tst r4, #0xff */
0x03140c01, /* tsteq r4, #0x100 */
0x1a000002, /* bne exit */
0xe2811008, /* add r1, r1, #0x8 */
0xe2533001, /* subs r3, r3, #1 */
0x1affffec, /* bne write */
/* exit: */
0xeafffffe, /* b exit */
};
/* flash write code */
if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
&write_algorithm) != ERROR_OK) {
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
uint8_t code[sizeof(str7x_flash_write_code)];
target_buffer_set_u32_array(target, code, ARRAY_SIZE(str7x_flash_write_code),
str7x_flash_write_code);
target_write_buffer(target, write_algorithm->address, sizeof(code), code);
/* memory buffer */
while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
if (buffer_size <= 256) {
/* we already allocated the writing code, but failed to get a
* buffer, free the algorithm */
target_free_working_area(target, write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
arm_algo.common_magic = ARM_COMMON_MAGIC;
arm_algo.core_mode = ARM_MODE_SVC;
arm_algo.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
init_reg_param(®_params[4], "r4", 32, PARAM_IN);
init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
while (count > 0) {
uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
target_write_buffer(target, source->address, thisrun_count * 8, buffer);
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
write_algorithm->address,
write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
10000, &arm_algo);
if (retval != ERROR_OK)
break;
if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00) {
retval = str7x_result(bank);
break;
}
buffer += thisrun_count * 8;
address += thisrun_count * 8;
count -= thisrun_count;
}
target_free_working_area(target, source);
target_free_working_area(target, write_algorithm);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
destroy_reg_param(®_params[4]);
destroy_reg_param(®_params[5]);
return retval;
}
int arc_mem_read(struct target *target, uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
int retval = ERROR_OK;
LOG_DEBUG("Read memory: addr=0x%08" PRIx32 ", size=%" PRIu32
", count=%" PRIu32, address, size, count);
if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* Sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_COMMAND_SYNTAX_ERROR;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
void *tunnel_he;
uint8_t *tunnel_te;
uint32_t words_to_read, bytes_to_read;
/* TODO: I think this function might be made much more clear if it
* would be splitted onto three based on size (4/2/1). That would
* duplicate some logic, but it would be much easier to understand it,
* those bit operations are just asking for a trouble. And they emulate
* size-specific logic, that is smart, but dangerous. */
/* Reads are word-aligned, so padding might be required if count > 1.
* NB: +3 is a padding for the last word (in case it's not aligned;
* addr&3 is a padding for the first word (since address can be
* unaligned as well). */
bytes_to_read = (count * size + 3 + (address & 3u)) & ~3u;
words_to_read = bytes_to_read >> 2;
tunnel_he = malloc(bytes_to_read);
tunnel_te = malloc(bytes_to_read);
if (!tunnel_he || !tunnel_te) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
/* We can read only word-aligned words. */
retval = arc_mem_read_block(target, address & ~3u, sizeof(uint32_t),
words_to_read, tunnel_he);
/* arc32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
/* endianness, but byte array should represent target endianness */
if (ERROR_OK == retval) {
switch (size) {
case 4:
target_buffer_set_u32_array(target, buffer, count,
tunnel_he);
break;
case 2:
target_buffer_set_u32_array(target, tunnel_te,
words_to_read, tunnel_he);
/* Will that work properly with count > 1 and big endian? */
memcpy(buffer, tunnel_te + (address & 3u),
count * sizeof(uint16_t));
break;
case 1:
target_buffer_set_u32_array(target, tunnel_te,
words_to_read, tunnel_he);
/* Will that work properly with count > 1 and big endian? */
memcpy(buffer, tunnel_te + (address & 3u), count);
break;
}
}
free(tunnel_he);
free(tunnel_te);
return retval;
}
int mips32_checksum_memory(struct target *target, uint32_t address,
uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
struct reg_param reg_params[2];
struct mips32_algorithm mips32_info;
/* see contrib/loaders/checksum/mips32.s for src */
static const uint32_t mips_crc_code[] = {
0x248C0000, /* addiu $t4, $a0, 0 */
0x24AA0000, /* addiu $t2, $a1, 0 */
0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */
0x10000010, /* beq $zero, $zero, ncomp */
0x240B0000, /* addiu $t3, $zero, 0 */
/* nbyte: */
0x81850000, /* lb $a1, ($t4) */
0x218C0001, /* addi $t4, $t4, 1 */
0x00052E00, /* sll $a1, $a1, 24 */
0x3C0204C1, /* lui $v0, 0x04c1 */
0x00852026, /* xor $a0, $a0, $a1 */
0x34471DB7, /* ori $a3, $v0, 0x1db7 */
0x00003021, /* addu $a2, $zero, $zero */
/* loop: */
0x00044040, /* sll $t0, $a0, 1 */
0x24C60001, /* addiu $a2, $a2, 1 */
0x28840000, /* slti $a0, $a0, 0 */
0x01074826, /* xor $t1, $t0, $a3 */
0x0124400B, /* movn $t0, $t1, $a0 */
0x28C30008, /* slti $v1, $a2, 8 */
0x1460FFF9, /* bne $v1, $zero, loop */
0x01002021, /* addu $a0, $t0, $zero */
/* ncomp: */
0x154BFFF0, /* bne $t2, $t3, nbyte */
0x256B0001, /* addiu $t3, $t3, 1 */
0x7000003F, /* sdbbp */
};
/* make sure we have a working area */
if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
/* convert mips crc code into a buffer in target endianness */
uint8_t mips_crc_code_8[sizeof(mips_crc_code)];
target_buffer_set_u32_array(target, mips_crc_code_8,
ARRAY_SIZE(mips_crc_code), mips_crc_code);
target_write_buffer(target, crc_algorithm->address, sizeof(mips_crc_code), mips_crc_code_8);
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
init_reg_param(®_params[0], "r4", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[0].value, 0, 32, address);
init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
buf_set_u32(reg_params[1].value, 0, 32, count);
int timeout = 20000 * (1 + (count / (1024 * 1024)));
int retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code) - 4), timeout,
&mips32_info);
if (retval == ERROR_OK)
*checksum = buf_get_u32(reg_params[0].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
target_free_working_area(target, crc_algorithm);
return retval;
}
