static int arm11_assert_reset(struct target *target) { struct arm11_common *arm11 = target_to_arm11(target); /* optionally catch reset vector */ if (target->reset_halt && !(arm11->vcr & 1)) CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1)); /* Issue some kind of warm reset. */ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { target_handle_event(target, TARGET_EVENT_RESET_ASSERT); } else if (jtag_get_reset_config() & RESET_HAS_SRST) { /* REVISIT handle "pulls" cases, if there's * hardware that needs them to work. */ jtag_add_reset(0, 1); } else { LOG_ERROR("%s: how to reset?", target_name(target)); return ERROR_FAIL; } /* registers are now invalid */ register_cache_invalidate(arm11->arm.core_cache); target->state = TARGET_RESET; return ERROR_OK; }
int arc_ocd_assert_reset(struct target *target) { struct arc32_common *arc32 = target_to_arc32(target); LOG_DEBUG("target->state: %s", target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { /* allow scripts to override the reset event */ target_handle_event(target, TARGET_EVENT_RESET_ASSERT); register_cache_invalidate(arc32->core_cache); /* An ARC target might be in halt state after reset, so * if script requested processor to resume, then it must * be manually started to ensure that this request * is satisfied. */ if (target->state == TARGET_HALTED && !target->reset_halt) { /* Resume the target and continue from the current * PC register value. */ LOG_DEBUG("Starting CPU execution after reset"); CHECK_RETVAL(target_resume(target, 1, 0, 0, 0)); } target->state = TARGET_RESET; return ERROR_OK; } /* some cores support connecting while srst is asserted * use that mode is it has been configured */ bool srst_asserted = false; if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_reset_config & RESET_SRST_NO_GATING)) { jtag_add_reset(0, 1); srst_asserted = true; } if (jtag_reset_config & RESET_HAS_SRST) { /* should issue a srst only, but we may have to assert trst as well */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) jtag_add_reset(1, 1); else if (!srst_asserted) jtag_add_reset(0, 1); } target->state = TARGET_RESET; jtag_add_sleep(50000); register_cache_invalidate(arc32->core_cache); if (target->reset_halt) CHECK_RETVAL(target_halt(target)); return ERROR_OK; }
int arc_ocd_assert_reset(struct target *target) { struct arc32_common *arc32 = target_to_arc32(target); LOG_DEBUG("target->state: %s", target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { /* allow scripts to override the reset event */ target_handle_event(target, TARGET_EVENT_RESET_ASSERT); register_cache_invalidate(arc32->core_cache); target->state = TARGET_RESET; return ERROR_OK; } /* some cores support connecting while srst is asserted * use that mode is it has been configured */ bool srst_asserted = false; if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_reset_config & RESET_SRST_NO_GATING)) { jtag_add_reset(0, 1); srst_asserted = true; } if (jtag_reset_config & RESET_HAS_SRST) { /* should issue a srst only, but we may have to assert trst as well */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) jtag_add_reset(1, 1); else if (!srst_asserted) jtag_add_reset(0, 1); } target->state = TARGET_RESET; jtag_add_sleep(50000); register_cache_invalidate(arc32->core_cache); if (target->reset_halt) CHECK_RETVAL(target_halt(target)); return ERROR_OK; }
static int arm11_assert_reset(struct target *target) { struct arm11_common *arm11 = target_to_arm11(target); if (!(target_was_examined(target))) { if (jtag_get_reset_config() & RESET_HAS_SRST) jtag_add_reset(0, 1); else { LOG_WARNING("Reset is not asserted because the target is not examined."); LOG_WARNING("Use a reset button or power cycle the target."); return ERROR_TARGET_NOT_EXAMINED; } } else { /* optionally catch reset vector */ if (target->reset_halt && !(arm11->vcr & 1)) CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1)); /* Issue some kind of warm reset. */ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) target_handle_event(target, TARGET_EVENT_RESET_ASSERT); else if (jtag_get_reset_config() & RESET_HAS_SRST) { /* REVISIT handle "pulls" cases, if there's * hardware that needs them to work. */ jtag_add_reset(0, 1); } else { LOG_ERROR("%s: how to reset?", target_name(target)); return ERROR_FAIL; } } /* registers are now invalid */ register_cache_invalidate(arm11->arm.core_cache); target->state = TARGET_RESET; return ERROR_OK; }