int disp_al_lcd_cfg(u32 screen_id, disp_panel_para * panel, panel_extend_para *extend_panel)
{
struct lcd_clk_info info;
al_priv.output_type[screen_id] = (u32)DISP_OUTPUT_TYPE_LCD;
al_priv.output_type[screen_id] = (u32)panel->lcd_if;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &info, panel);
tcon0_set_dclk_div(screen_id, info.tcon_div);
if(0 != tcon0_cfg(screen_id, panel))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
tcon0_cfg_ext(screen_id, extend_panel);
if(LCD_IF_DSI == panel->lcd_if) {
#if defined(SUPPORT_DSI)
if(0 != dsi_cfg(screen_id, panel)) {
DE_WRN("dsi cfg fail!\n");
}
#endif
}
return 0;
}
__s32 BSP_disp_tv_open(__u32 sel)
{
if((!(gdisp.screen[sel].status & TV_ON)))
{
__disp_tv_mode_t tv_mod;
__panel_para_t para;
memset(¶, 0, sizeof(__panel_para_t));
tv_mod = gdisp.screen[sel].tv_mode;
lcdc_clk_on(sel, 0, 0);
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_TV, tv_mod);
lcdc_clk_on(sel, 0, 1);
drc_clk_open(sel,0);
tcon_init(sel);
image_clk_on(sel, 1);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
BSP_disp_set_output_csc(sel, DISP_OUT_CSC_TYPE_LCD, BSP_disp_drc_get_input_csc(sel)); //LCD -->GM7121, rgb fmt
DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod));
DE_BE_Output_Select(sel, sel);
disp_tv_get_timing(¶, tv_mod);
tcon0_cfg(sel,(__panel_para_t*)¶);
tcon0_src_select(sel,4);
if(gdisp.screen[sel].tv_ops.tv_power_on)
{
gdisp.screen[sel].tv_ops.tv_power_on(1);
msleep(500);
}
disp_tv_pin_cfg(1);
tcon0_open(sel,(__panel_para_t*)¶);
if(gdisp.screen[sel].tv_ops.tv_open)
{
gdisp.screen[sel].tv_ops.tv_open();
}
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod);
gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod);
gdisp.screen[sel].status = TV_ON;
gdisp.screen[sel].lcdc_status |= LCDC_TCON0_USED;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV;
gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_LCD;//LCD -->GM7121, rgb fmt
if(BSP_disp_cmu_get_enable(sel) ==1)
{
IEP_CMU_Set_Imgsize(sel, BSP_disp_get_screen_width(sel), BSP_disp_get_screen_height(sel));
}
Disp_set_out_interlace(sel);
#ifdef __LINUX_OSAL__
Display_set_fb_timming(sel);
#endif
tcon0_src_select(sel,0);
}
return DIS_SUCCESS;
}
int disp_al_vdevice_cfg(u32 screen_id, disp_video_timings *video_info, disp_vdevice_interface_para *para)
{
struct lcd_clk_info clk_info;
disp_panel_para info;
al_priv.output_type[screen_id] = (u32)DISP_OUTPUT_TYPE_LCD;
al_priv.output_mode[screen_id] = (u32)para->intf;
memset(&info, 0, sizeof(disp_panel_para));
info.lcd_if = para->intf;
info.lcd_x = video_info->x_res;
info.lcd_y = video_info->y_res;
info.lcd_hv_if = (disp_lcd_hv_if)para->sub_intf;
info.lcd_dclk_freq = video_info->pixel_clk;
info.lcd_ht = video_info->hor_total_time;
info.lcd_hbp = video_info->hor_back_porch + video_info->hor_sync_time;
info.lcd_hspw = video_info->hor_sync_time;
info.lcd_vt = video_info->ver_total_time;
info.lcd_vbp = video_info->ver_back_porch + video_info->ver_sync_time;
info.lcd_vspw = video_info->ver_sync_time;
info.lcd_hv_syuv_fdly = para->fdelay;
if(LCD_HV_IF_CCIR656_2CYC == info.lcd_hv_if)
info.lcd_hv_syuv_seq = para->sequence;
else
info.lcd_hv_srgb_seq = para->sequence;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &clk_info, &info);
clk_info.tcon_div = 11;//fixme
tcon0_set_dclk_div(screen_id, clk_info.tcon_div);
if(0 != tcon0_cfg(screen_id, &info))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
return 0;
}
int disp_al_lcd_cfg(u32 screen_id, disp_panel_para * panel)
{
struct lcd_clk_info info;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &info, panel);
DE_INF("lcd %d clk_div=%d!\n", screen_id, info.tcon_div);
tcon0_set_dclk_div(screen_id, info.tcon_div);
if(0 != tcon0_cfg(screen_id, panel))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
if(LCD_IF_DSI == panel->lcd_if) {
#if defined(SUPPORT_DSI)
if(0 != dsi_cfg(screen_id, panel)) {
DE_WRN("dsi cfg fail!\n");
}
#endif
}
return 0;
}
