int __init roth_soctherm_init(void) { tegra_add_vc_trips(roth_soctherm_data.therm[THERM_CPU].trips, &roth_soctherm_data.therm[THERM_CPU].num_trips); return tegra11_soctherm_init(&roth_soctherm_data); }
int __init tegratab_soctherm_init(void) { tegra_platform_edp_init(tegratab_soctherm_data.therm[THERM_CPU].trips, &tegratab_soctherm_data.therm[THERM_CPU].num_trips, 8000); /* edp temperature margin */ tegra_add_tj_trips(tegratab_soctherm_data.therm[THERM_CPU].trips, &tegratab_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_vc_trips(tegratab_soctherm_data.therm[THERM_CPU].trips, &tegratab_soctherm_data.therm[THERM_CPU].num_trips); return tegra11_soctherm_init(&tegratab_soctherm_data); }
int __init macallan_soctherm_init(void) { struct board_info board_info; tegra_get_board_info(&board_info); if (board_info.board_id == BOARD_E1545) tegra_add_cdev_trips(macallan_soctherm_data.therm[THERM_CPU].trips, &macallan_soctherm_data.therm[THERM_CPU].num_trips); tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips, &macallan_soctherm_data.therm[THERM_CPU].num_trips, 6000); /* edp temperature margin */ tegra_add_tj_trips(macallan_soctherm_data.therm[THERM_CPU].trips, &macallan_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_vc_trips(macallan_soctherm_data.therm[THERM_CPU].trips, &macallan_soctherm_data.therm[THERM_CPU].num_trips); return tegra11_soctherm_init(&macallan_soctherm_data); }
int __init dalmore_soctherm_init(void) { struct board_info board_info; tegra_get_board_info(&board_info); if (!(board_info.board_id == BOARD_E1611 || board_info.board_id == BOARD_P2454)) dalmore_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663; tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips, &dalmore_soctherm_data.therm[THERM_CPU].num_trips, 6000); /* edp temperature margin */ tegra_add_tj_trips(dalmore_soctherm_data.therm[THERM_CPU].trips, &dalmore_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_vc_trips(dalmore_soctherm_data.therm[THERM_CPU].trips, &dalmore_soctherm_data.therm[THERM_CPU].num_trips); return tegra11_soctherm_init(&dalmore_soctherm_data); }
int __init laguna_soctherm_init(void) { tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips, &laguna_soctherm_data.therm[THERM_CPU].num_trips, 7000); /* edp temperature margin */ tegra_platform_gpu_edp_init( laguna_soctherm_data.therm[THERM_GPU].trips, &laguna_soctherm_data.therm[THERM_GPU].num_trips, 7000); tegra_add_cpu_vmax_trips(laguna_soctherm_data.therm[THERM_CPU].trips, &laguna_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_tgpu_trips(laguna_soctherm_data.therm[THERM_GPU].trips, &laguna_soctherm_data.therm[THERM_GPU].num_trips); tegra_add_vc_trips(laguna_soctherm_data.therm[THERM_CPU].trips, &laguna_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_core_vmax_trips(laguna_soctherm_data.therm[THERM_PLL].trips, &laguna_soctherm_data.therm[THERM_PLL].num_trips); return tegra11_soctherm_init(&laguna_soctherm_data); }
static int flounder_nct72_init(void) { s32 base_cp, shft_cp; u32 base_ft, shft_ft; int nct72_port = TEGRA_GPIO_PI6; int ret = 0; int i; struct thermal_trip_info *trip_state; /* raise NCT's thresholds if soctherm CP,FT fuses are ok */ if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) && (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) { flounder_nct72_pdata.sensors[EXT].shutdown_limit += 20; for (i = 0; i < flounder_nct72_pdata.sensors[EXT].num_trips; i++) { trip_state = &flounder_nct72_pdata.sensors[EXT].trips[i]; if (!strncmp(trip_state->cdev_type, "cpu-balanced", THERMAL_NAME_LENGTH)) { trip_state->cdev_type = "_none_"; break; } } } else { tegra_platform_edp_init( flounder_nct72_pdata.sensors[EXT].trips, &flounder_nct72_pdata.sensors[EXT].num_trips, 12000); /* edp temperature margin */ tegra_add_cpu_vmax_trips( flounder_nct72_pdata.sensors[EXT].trips, &flounder_nct72_pdata.sensors[EXT].num_trips); tegra_add_tgpu_trips( flounder_nct72_pdata.sensors[EXT].trips, &flounder_nct72_pdata.sensors[EXT].num_trips); tegra_add_vc_trips( flounder_nct72_pdata.sensors[EXT].trips, &flounder_nct72_pdata.sensors[EXT].num_trips); tegra_add_core_vmax_trips( flounder_nct72_pdata.sensors[EXT].trips, &flounder_nct72_pdata.sensors[EXT].num_trips); } tegra_add_all_vmin_trips(flounder_nct72_pdata.sensors[EXT].trips, &flounder_nct72_pdata.sensors[EXT].num_trips); flounder_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port); ret = gpio_request(nct72_port, "temp_alert"); if (ret < 0) return ret; ret = gpio_direction_input(nct72_port); if (ret < 0) { pr_info("%s: calling gpio_free(nct72_port)", __func__); gpio_free(nct72_port); } i2c_register_board_info(0, flounder_i2c_nct72_board_info, ARRAY_SIZE(flounder_i2c_nct72_board_info)); return ret; }
static int ardbeg_nct72_init(void) { s32 base_cp, shft_cp; u32 base_ft, shft_ft; int nct72_port = TEGRA_GPIO_PI6; int ret = 0; int i; struct thermal_trip_info *trip_state; struct board_info board_info; tegra_get_board_info(&board_info); /* raise NCT's thresholds if soctherm CP,FT fuses are ok */ if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) && (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) { ardbeg_nct72_pdata.shutdown_ext_limit += 20; for (i = 0; i < ardbeg_nct72_pdata.num_trips; i++) { trip_state = &ardbeg_nct72_pdata.trips[i]; if (!strncmp(trip_state->cdev_type, "cpu-balanced", THERMAL_NAME_LENGTH)) { trip_state->cdev_type = "_none_"; break; } } } else { tegra_platform_edp_init(ardbeg_nct72_pdata.trips, &ardbeg_nct72_pdata.num_trips, 12000); /* edp temperature margin */ tegra_add_cpu_vmax_trips(ardbeg_nct72_pdata.trips, &ardbeg_nct72_pdata.num_trips); tegra_add_tgpu_trips(ardbeg_nct72_pdata.trips, &ardbeg_nct72_pdata.num_trips); tegra_add_vc_trips(ardbeg_nct72_pdata.trips, &ardbeg_nct72_pdata.num_trips); tegra_add_core_vmax_trips(ardbeg_nct72_pdata.trips, &ardbeg_nct72_pdata.num_trips); } tegra_add_all_vmin_trips(ardbeg_nct72_pdata.trips, &ardbeg_nct72_pdata.num_trips); ardbeg_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port); ret = gpio_request(nct72_port, "temp_alert"); if (ret < 0) return ret; ret = gpio_direction_input(nct72_port); if (ret < 0) { pr_info("%s: calling gpio_free(nct72_port)", __func__); gpio_free(nct72_port); } /* ardbeg has thermal sensor on GEN2-I2C i.e. instance 1 */ if (board_info.board_id == BOARD_PM358 || board_info.board_id == BOARD_PM359 || board_info.board_id == BOARD_PM370 || board_info.board_id == BOARD_PM374 || board_info.board_id == BOARD_PM363) i2c_register_board_info(1, laguna_i2c_nct72_board_info, ARRAY_SIZE(laguna_i2c_nct72_board_info)); else if (board_info.board_id == BOARD_PM375 || board_info.board_id == BOARD_PM377) i2c_register_board_info(0, laguna_i2c_nct72_board_info, ARRAY_SIZE(laguna_i2c_nct72_board_info)); else i2c_register_board_info(1, ardbeg_i2c_nct72_board_info, ARRAY_SIZE(ardbeg_i2c_nct72_board_info)); return ret; }
int __init ardbeg_soctherm_init(void) { s32 base_cp, shft_cp; u32 base_ft, shft_ft; struct board_info pmu_board_info; struct board_info board_info; tegra_get_board_info(&board_info); if (board_info.board_id == BOARD_E1923 || board_info.board_id == BOARD_E1922) { memcpy(ardbeg_soctherm_data.therm, ardbeg_therm_pop, sizeof(ardbeg_therm_pop)); } /* do this only for supported CP,FT fuses */ if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) && (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) { tegra_platform_edp_init( ardbeg_soctherm_data.therm[THERM_CPU].trips, &ardbeg_soctherm_data.therm[THERM_CPU].num_trips, 7000); /* edp temperature margin */ tegra_platform_gpu_edp_init( ardbeg_soctherm_data.therm[THERM_GPU].trips, &ardbeg_soctherm_data.therm[THERM_GPU].num_trips, 7000); tegra_add_cpu_vmax_trips( ardbeg_soctherm_data.therm[THERM_CPU].trips, &ardbeg_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_tgpu_trips( ardbeg_soctherm_data.therm[THERM_GPU].trips, &ardbeg_soctherm_data.therm[THERM_GPU].num_trips); tegra_add_vc_trips( ardbeg_soctherm_data.therm[THERM_CPU].trips, &ardbeg_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_core_vmax_trips( ardbeg_soctherm_data.therm[THERM_PLL].trips, &ardbeg_soctherm_data.therm[THERM_PLL].num_trips); } if (board_info.board_id == BOARD_P1761 || board_info.board_id == BOARD_E1784 || board_info.board_id == BOARD_E1971 || board_info.board_id == BOARD_E1991 || board_info.board_id == BOARD_E1922) { tegra_add_cpu_vmin_trips( ardbeg_soctherm_data.therm[THERM_CPU].trips, &ardbeg_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_gpu_vmin_trips( ardbeg_soctherm_data.therm[THERM_GPU].trips, &ardbeg_soctherm_data.therm[THERM_GPU].num_trips); tegra_add_core_vmin_trips( ardbeg_soctherm_data.therm[THERM_PLL].trips, &ardbeg_soctherm_data.therm[THERM_PLL].num_trips); } tegra_get_pmu_board_info(&pmu_board_info); if ((pmu_board_info.board_id == BOARD_E1733) || (pmu_board_info.board_id == BOARD_E1734)) ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722; else if (pmu_board_info.board_id == BOARD_E1735 || pmu_board_info.board_id == BOARD_E1736 || pmu_board_info.board_id == BOARD_E1769 || pmu_board_info.board_id == BOARD_P1761 || pmu_board_info.board_id == BOARD_E1936) ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_palmas; else pr_warn("soctherm THERMTRIP not supported on PMU (BOARD_E%d)\n", pmu_board_info.board_id); /* Enable soc_therm OC throttling on selected platforms */ switch (pmu_board_info.board_id) { case BOARD_P1761: memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC4], &battery_oc_throttle, sizeof(battery_oc_throttle)); memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC1], &voltmon_throttle, sizeof(voltmon_throttle)); break; default: break; } return tegra11_soctherm_init(&ardbeg_soctherm_data); }