int tegra_dc_ext_set_cursor(struct tegra_dc_ext_user *user,
struct tegra_dc_ext_cursor *args)
{
struct tegra_dc_ext *ext = user->ext;
struct tegra_dc *dc = ext->dc;
u32 val;
bool enable;
int ret;
mutex_lock(&ext->cursor.lock);
if (ext->cursor.user != user) {
ret = -EACCES;
goto unlock;
}
if (!ext->enabled) {
ret = -ENXIO;
goto unlock;
}
enable = !!(args->flags & TEGRA_DC_EXT_CURSOR_FLAGS_VISIBLE);
mutex_lock(&dc->lock);
tegra_dc_get(dc);
val = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
if (!!(val & CURSOR_ENABLE) != enable) {
val &= ~CURSOR_ENABLE;
if (enable)
val |= CURSOR_ENABLE;
tegra_dc_writel(dc, val, DC_DISP_DISP_WIN_OPTIONS);
}
tegra_dc_writel(dc, CURSOR_POSITION(args->x, args->y),
DC_DISP_CURSOR_POSITION);
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
/* TODO: need to sync here? hopefully can avoid this, but need to
* figure out interaction w/ rest of GENERAL_ACT_REQ */
tegra_dc_put(dc);
mutex_unlock(&dc->lock);
mutex_unlock(&ext->cursor.lock);
return 0;
unlock:
mutex_unlock(&ext->cursor.lock);
return ret;
}
int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
{
mutex_lock(&dc->lock);
if (!dc->enabled) {
mutex_unlock(&dc->lock);
return -EFAULT;
}
tegra_dc_get(dc);
tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
DC_CMD_DISPLAY_WINDOW_HEADER);
tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
tegra_dc_put(dc);
mutex_unlock(&dc->lock);
return 0;
}
static ssize_t nvsd_registers_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
struct device *dev = container_of((kobj->parent), struct device, kobj);
struct platform_device *ndev = to_platform_device(dev);
struct tegra_dc *dc = platform_get_drvdata(ndev);
ssize_t res = 0;
mutex_lock(&dc->lock);
if (!dc->enabled) {
mutex_unlock(&dc->lock);
return -ENODEV;
}
tegra_dc_get(dc);
mutex_unlock(&dc->lock);
NVSD_PRINT_REG(DC_DISP_SD_CONTROL);
NVSD_PRINT_REG(DC_DISP_SD_CSC_COEFF);
NVSD_PRINT_REG_ARRAY(DC_DISP_SD_LUT);
NVSD_PRINT_REG(DC_DISP_SD_FLICKER_CONTROL);
NVSD_PRINT_REG(DC_DISP_SD_PIXEL_COUNT);
NVSD_PRINT_REG_ARRAY(DC_DISP_SD_HISTOGRAM);
NVSD_PRINT_REG(DC_DISP_SD_BL_PARAMETERS);
NVSD_PRINT_REG_ARRAY(DC_DISP_SD_BL_TF);
NVSD_PRINT_REG(DC_DISP_SD_BL_CONTROL);
NVSD_PRINT_REG(DC_DISP_SD_HW_K_VALUES);
NVSD_PRINT_REG(DC_DISP_SD_MAN_K_VALUES);
#ifdef CONFIG_TEGRA_SD_GEN2
NVSD_PRINT_REG(DC_DISP_SD_K_LIMIT);
NVSD_PRINT_REG(DC_DISP_SD_WINDOW_POSITION);
NVSD_PRINT_REG(DC_DISP_SD_WINDOW_SIZE);
NVSD_PRINT_REG(DC_DISP_SD_SOFT_CLIPPING);
NVSD_PRINT_REG(DC_DISP_SD_SMOOTH_K);
#endif
tegra_dc_put(dc);
mutex_unlock(&dc->lock);
return res;
}
int tegra_dc_ext_cursor_clip(struct tegra_dc_ext_user *user,
int *args)
{
struct tegra_dc_ext *ext = user->ext;
struct tegra_dc *dc = ext->dc;
int ret;
unsigned long reg_val;
mutex_lock(&ext->cursor.lock);
if (ext->cursor.user != user) {
ret = -EACCES;
goto unlock;
}
if (!ext->enabled) {
ret = -ENXIO;
goto unlock;
}
mutex_lock(&dc->lock);
tegra_dc_get(dc);
reg_val = tegra_dc_readl(dc, DC_DISP_CURSOR_START_ADDR);
reg_val &= ~CURSOR_CLIP_SHIFT_BITS(3); /* Clear out the old value */
tegra_dc_writel(dc, reg_val | CURSOR_CLIP_SHIFT_BITS(*args),
DC_DISP_CURSOR_START_ADDR);
tegra_dc_put(dc);
mutex_unlock(&dc->lock);
mutex_unlock(&ext->cursor.lock);
return 0;
unlock:
mutex_unlock(&ext->cursor.lock);
return ret;
}
static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
{
struct tegra_dc_win *win = &dc->windows[win_idx];
mutex_lock(&dc->lock);
tegra_dc_get(dc);
if (!dc->enabled) {
tegra_dc_put(dc);
mutex_unlock(&dc->lock);
return -EFAULT;
}
if (fbovr > 0)
win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
else if (fbovr == 0)
win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
else
win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
DC_CMD_DISPLAY_WINDOW_HEADER);
tegra_dc_set_lut(dc, win);
mutex_unlock(&dc->lock);
tegra_dc_update_windows(&win, 1);
tegra_dc_sync_windows(&win, 1);
tegra_dc_put(dc);
return 0;
}
static ssize_t nvsd_settings_store(struct kobject *kobj,
struct kobj_attribute *attr, const char *buf, size_t count)
{
struct device *dev = container_of((kobj->parent), struct device, kobj);
struct platform_device *ndev = to_platform_device(dev);
struct tegra_dc *dc = platform_get_drvdata(ndev);
struct tegra_dc_sd_settings *sd_settings = dc->out->sd_settings;
ssize_t res = count;
bool settings_updated = false;
long int result;
int err;
if (sd_settings) {
if (IS_NVSD_ATTR(enable)) {
if (sd_settings->phase_in_settings) {
err = strict_strtol(buf, 10, &result);
if (err)
return err;
if (nvsd_update_enable(sd_settings, result))
nvsd_check_and_update(1, 1, enable);
} else {
nvsd_check_and_update(0, 1, enable);
}
} else if (IS_NVSD_ATTR(aggressiveness)) {
err = strict_strtol(buf, 10, &result);
if (err)
return err;
if (nvsd_update_agg(sd_settings, result)
&& !sd_settings->phase_in_settings)
settings_updated = true;
} else if (IS_NVSD_ATTR(phase_in_settings)) {
nvsd_check_and_update(0, 1, phase_in_settings);
} else if (IS_NVSD_ATTR(phase_in_adjustments)) {
nvsd_check_and_update(0, 1, phase_in_adjustments);
} else if (IS_NVSD_ATTR(bin_width)) {
nvsd_check_and_update(-1, 8, bin_width);
} else if (IS_NVSD_ATTR(hw_update_delay)) {
nvsd_check_and_update(0, 2, hw_update_delay);
} else if (IS_NVSD_ATTR(use_vid_luma)) {
nvsd_check_and_update(0, 1, use_vid_luma);
} else if (IS_NVSD_ATTR(coeff)) {
int ele[3], i = 0, num = 3;
nvsd_get_multi(ele, num, i, 0, 15);
if (i == num) {
sd_settings->coeff.r = ele[0];
sd_settings->coeff.g = ele[1];
sd_settings->coeff.b = ele[2];
settings_updated = true;
} else {
res = -EINVAL;
}
} else if (IS_NVSD_ATTR(blp_time_constant)) {
nvsd_check_and_update(0, 1024, blp.time_constant);
} else if (IS_NVSD_ATTR(blp_step)) {
nvsd_check_and_update(0, 255, blp.step);
} else if (IS_NVSD_ATTR(fc_time_limit)) {
nvsd_check_and_update(0, 255, fc.time_limit);
} else if (IS_NVSD_ATTR(fc_threshold)) {
nvsd_check_and_update(0, 255, fc.threshold);
#ifdef CONFIG_TEGRA_SD_GEN2
} else if (IS_NVSD_ATTR(k_limit_enable)) {
nvsd_check_and_update(0, 1, k_limit_enable);
} else if (IS_NVSD_ATTR(k_limit)) {
nvsd_check_and_update(128, 255, k_limit);
} else if (IS_NVSD_ATTR(sd_window_enable)) {
nvsd_check_and_update(0, 1, sd_window_enable);
} else if (IS_NVSD_ATTR(sd_window)) {
int ele[4], i = 0, num = 4;
nvsd_get_multi(ele, num, i, 0, LONG_MAX);
if (i == num) {
sd_settings->sd_window.h_position = ele[0];
sd_settings->sd_window.v_position = ele[1];
sd_settings->sd_window.h_size = ele[2];
sd_settings->sd_window.v_size = ele[3];
settings_updated = true;
} else {
res = -EINVAL;
}
} else if (IS_NVSD_ATTR(soft_clipping_enable)) {
nvsd_check_and_update(0, 1, soft_clipping_enable);
} else if (IS_NVSD_ATTR(soft_clipping_threshold)) {
nvsd_check_and_update(0, 255, soft_clipping_threshold);
} else if (IS_NVSD_ATTR(soft_clipping_correction)) {
nvsd_check_and_update(0, 1, soft_clipping_correction);
} else if (IS_NVSD_ATTR(smooth_k_enable)) {
nvsd_check_and_update(0, 1, smooth_k_enable);
} else if (IS_NVSD_ATTR(smooth_k_incr)) {
nvsd_check_and_update(0, 16320, smooth_k_incr);
} else if (IS_NVSD_ATTR(use_vpulse2)) {
nvsd_check_and_update(0, 1, use_vpulse2);
#endif
} else if (IS_NVSD_ATTR(lut)) {
if (nvsd_lut_store(sd_settings, buf))
res = -EINVAL;
else
settings_updated = true;
} else if (IS_NVSD_ATTR(bltf)) {
if (nvsd_bltf_store(sd_settings, buf))
res = -EINVAL;
else
settings_updated = true;
} else {
res = -EINVAL;
}
/* Re-init if our settings were updated. */
if (settings_updated) {
mutex_lock(&dc->lock);
if (!dc->enabled) {
mutex_unlock(&dc->lock);
return -ENODEV;
}
tegra_dc_get(dc);
nvsd_init(dc, sd_settings);
tegra_dc_put(dc);
mutex_unlock(&dc->lock);
/* Update backlight state IFF we're disabling! */
if (!sd_settings->enable && sd_settings->bl_device) {
/* Do the actual brightness update outside of
* the mutex */
struct backlight_device *bl =
sd_settings->bl_device;
if (bl)
backlight_update_status(bl);
}
}
} else {
/* This shouldn't be reachable. But just in case... */
res = -EINVAL;
}
return res;
}
int tegra_dc_ext_set_cursor_image(struct tegra_dc_ext_user *user,
struct tegra_dc_ext_cursor_image *args)
{
struct tegra_dc_ext *ext = user->ext;
struct tegra_dc *dc = ext->dc;
struct nvmap_handle_ref *handle, *old_handle;
dma_addr_t phys_addr;
u32 size;
int ret;
if (!user->nvmap)
return -EFAULT;
size = TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE(args->flags);
#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
if (size != TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_32x32 &&
size != TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_64x64)
return -EINVAL;
#else
if (size != TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_32x32 &&
size != TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_64x64 &&
size != TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_128x128 &&
size != TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_256x256)
return -EINVAL;
#endif
#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
if (args->flags & TEGRA_DC_EXT_CURSOR_FLAGS_RGBA_NORMAL)
return -EINVAL;
#endif
mutex_lock(&ext->cursor.lock);
if (ext->cursor.user != user) {
ret = -EACCES;
goto unlock;
}
if (!ext->enabled) {
ret = -ENXIO;
goto unlock;
}
old_handle = ext->cursor.cur_handle;
ret = tegra_dc_ext_pin_window(user, args->buff_id, &handle, &phys_addr);
if (ret)
goto unlock;
ext->cursor.cur_handle = handle;
mutex_lock(&dc->lock);
tegra_dc_get(dc);
set_cursor_image_hw(dc, args, phys_addr);
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_put(dc);
/* XXX sync here? */
mutex_unlock(&dc->lock);
mutex_unlock(&ext->cursor.lock);
if (old_handle) {
nvmap_unpin(ext->nvmap, old_handle);
nvmap_free(ext->nvmap, old_handle);
}
return 0;
unlock:
mutex_unlock(&ext->cursor.lock);
return ret;
}
int esc_mods_tegra_dc_setup_sd(struct file *fp,
struct MODS_TEGRA_DC_SETUP_SD *args)
{
int i;
struct tegra_dc *dc = tegra_dc_get_dc(args->head);
struct tegra_dc_sd_settings *sd_settings = dc->out->sd_settings;
#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
u32 val;
#endif
u32 bw_idx;
LOG_ENT();
BUG_ON(args->head > TEGRA_MAX_DC);
sd_settings->enable = args->enable ? 1 : 0;
sd_settings->use_auto_pwm = false;
sd_settings->hw_update_delay = 0;
sd_settings->aggressiveness = args->aggressiveness;
sd_settings->bin_width = (1 << args->bin_width_log2);
sd_settings->phase_in_settings = 0;
sd_settings->phase_in_adjustments = 0;
sd_settings->cmd = 0;
sd_settings->final_agg = args->aggressiveness;
sd_settings->cur_agg_step = 0;
sd_settings->phase_settings_step = 0;
sd_settings->phase_adj_step = 0;
sd_settings->num_phase_in_steps = 0;
sd_settings->agg_priorities.agg[0] = args->aggressiveness;
sd_settings->use_vid_luma = args->use_vid_luma;
sd_settings->coeff.r = args->csc_r;
sd_settings->coeff.g = args->csc_g;
sd_settings->coeff.b = args->csc_b;
sd_settings->k_limit_enable = (args->klimit != 0);
sd_settings->k_limit = args->klimit;
sd_settings->sd_window_enable = true;
sd_settings->sd_window.h_position = args->win_x;
sd_settings->sd_window.v_position = args->win_y;
sd_settings->sd_window.h_size = args->win_w;
sd_settings->sd_window.v_size = args->win_h;
sd_settings->soft_clipping_enable = true;
sd_settings->soft_clipping_threshold = args->soft_clipping_threshold;
sd_settings->smooth_k_enable = (args->smooth_k_inc != 0);
sd_settings->smooth_k_incr = args->smooth_k_inc;
sd_settings->sd_proc_control = false;
sd_settings->soft_clipping_correction = false;
sd_settings->use_vpulse2 = false;
sd_settings->fc.time_limit = 0;
sd_settings->fc.threshold = 0;
sd_settings->blp.time_constant = 1024;
sd_settings->blp.step = 0;
#ifdef CONFIG_TEGRA_SD_GEN2
bw_idx = 0;
#else
bw_idx = args->bin_width_log2;
#endif
for (i = 0; i < MODS_TEGRA_DC_SETUP_BLTF_SIZE; i++) {
sd_settings->bltf[bw_idx][i/4][i%4] =
args->bltf[i];
}
for (i = 0; i < MODS_TEGRA_DC_SETUP_SD_LUT_SIZE; i++) {
sd_settings->lut[bw_idx][i].r =
args->lut[i] & 0xff;
sd_settings->lut[bw_idx][i].g =
(args->lut[i] >> 8) & 0xff;
sd_settings->lut[bw_idx][i].b =
(args->lut[i] >> 16) & 0xff;
}
#if defined(CONFIG_TEGRA_NVSD)
nvsd_init(dc, sd_settings);
#endif
#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
tegra_dc_io_start(dc);
val = tegra_dc_readl(dc, DC_DISP_SD_CONTROL);
val &= ~SD_KINIT_BIAS(0);
val &= ~SD_CORRECTION_MODE_MAN;
tegra_dc_writel(dc, val | SD_KINIT_BIAS(args->k_init_bias),
DC_DISP_SD_CONTROL);
tegra_dc_io_end(dc);
#endif
if (dc->enabled) {
mutex_lock(&dc->lock);
tegra_dc_get(dc);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_put(dc);
mutex_unlock(&dc->lock);
}
LOG_EXT();
return 0;
}