static bool _tegra_dc_enable(struct tegra_dc *dc) { if (dc->mode.pclk == 0) return false; tegra_dc_io_start(dc); if (dc->out && dc->out->enable) dc->out->enable(); tegra_dc_setup_clk(dc, dc->clk); clk_enable(dc->clk); clk_enable(dc->emc_clk); tegra_periph_reset_deassert(dc->clk); msleep(10); enable_irq(dc->irq); tegra_dc_init(dc); if (dc->out_ops && dc->out_ops->enable) dc->out_ops->enable(dc); /* force a full blending update */ dc->blend.z[0] = -1; tegra_dc_ext_enable(dc->ext); return true; }
static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc) { bool ret = true; if (dc->out->enable) dc->out->enable(); tegra_dc_setup_clk(dc, dc->clk); tegra_dc_clk_enable(dc); if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) { mutex_lock(&tegra_dcs[1]->lock); disable_irq(tegra_dcs[1]->irq); } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) { mutex_lock(&tegra_dcs[0]->lock); disable_irq(tegra_dcs[0]->irq); } msleep(5); tegra_periph_reset_assert(dc->clk); msleep(2); #ifdef CONFIG_TEGRA_SILICON_PLATFORM tegra_periph_reset_deassert(dc->clk); msleep(1); #endif if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) { enable_dc_irq(tegra_dcs[1]->irq); mutex_unlock(&tegra_dcs[1]->lock); } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) { enable_dc_irq(tegra_dcs[0]->irq); mutex_unlock(&tegra_dcs[0]->lock); } enable_dc_irq(dc->irq); if (tegra_dc_init(dc)) { dev_err(&dc->ndev->dev, "cannot initialize\n"); ret = false; } if (dc->out_ops && dc->out_ops->enable) dc->out_ops->enable(dc); if (dc->out->postpoweron) dc->out->postpoweron(); /* force a full blending update */ dc->blend.z[0] = -1; tegra_dc_ext_enable(dc->ext); if (!ret) { dev_err(&dc->ndev->dev, "initialization failed,disabling"); _tegra_dc_controller_disable(dc); } trace_printk("%s:reset enable\n", dc->ndev->name); return ret; }
static bool _tegra_dc_controller_enable(struct tegra_dc *dc) { int failed_init = 0; if (dc->out->enable) dc->out->enable(); tegra_dc_setup_clk(dc, dc->clk); tegra_dc_clk_enable(dc); /* do not accept interrupts during initialization */ tegra_dc_writel(dc, 0, DC_CMD_INT_MASK); enable_dc_irq(dc->irq); failed_init = tegra_dc_init(dc); if (failed_init) { tegra_dc_writel(dc, 0, DC_CMD_INT_MASK); disable_irq(dc->irq); tegra_dc_clear_bandwidth(dc); tegra_dc_clk_disable(dc); if (dc->out && dc->out->disable) dc->out->disable(); return false; } if (dc->out_ops && dc->out_ops->enable) dc->out_ops->enable(dc); /* force a full blending update */ dc->blend.z[0] = -1; tegra_dc_ext_enable(dc->ext); trace_printk("%s:enable\n", dc->ndev->name); tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL); tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); if (dc->out->postpoweron) dc->out->postpoweron(); return true; }
/* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ void display_startup(device_t dev) { struct soc_nvidia_tegra124_config *config = dev->chip_info; struct display_controller *disp_ctrl = (void *)config->display_controller; struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE; struct tegra_dc *dc = &dc_data; u32 plld_rate; /* init dc */ dc->base = (void *)TEGRA_ARM_DISPLAYA; dc->config = config; config->dc_data = dc; /* Note dp_init may read EDID and change some config values. */ dp_init(config); /* should probably just make it all MiB ... in future */ u32 framebuffer_size_mb = config->framebuffer_size / MiB; u32 framebuffer_base_mb= config->framebuffer_base / MiB; /* light it all up */ /* This one may have been done in romstage but that's ok for now. */ if (config->panel_vdd_gpio){ gpio_output(config->panel_vdd_gpio, 1); printk(BIOS_SPEW,"%s: panel_vdd setting gpio %08x to %d\n", __func__, config->panel_vdd_gpio, 1); } udelay(config->vdd_delay_ms * 1000); if (config->backlight_vdd_gpio){ gpio_output(config->backlight_vdd_gpio, 1); printk(BIOS_SPEW,"%s: backlight vdd setting gpio %08x to %d\n", __func__, config->backlight_vdd_gpio, 1); } if (config->lvds_shutdown_gpio){ gpio_output(config->lvds_shutdown_gpio, 0); printk(BIOS_SPEW,"%s: lvds shutdown setting gpio %08x to %d\n", __func__, config->lvds_shutdown_gpio, 0); } if (framebuffer_size_mb == 0){ framebuffer_size_mb = ALIGN_UP(config->xres * config->yres * (config->framebuffer_bits_per_pixel / 8), MiB)/MiB; } if (! framebuffer_base_mb) framebuffer_base_mb = fb_base_mb(); config->framebuffer_size = framebuffer_size_mb * MiB; config->framebuffer_base = framebuffer_base_mb * MiB; mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, config->cache_policy); printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb, framebuffer_base_mb + framebuffer_size_mb); /* GPIO magic here if needed to start powering up things. You * really only want to enable vdd, wait a bit, and then enable * the panel. However ... the timings in the tegra20 dts make * no sense to me. I'm pretty sure they're wrong. * The panel_vdd is done in the romstage, so we need only * light things up here once we're sure it's all working. */ /* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the * update_display_mode() for detail. */ plld_rate = clock_display(config->pixel_clock * 2); if (plld_rate == 0) { printk(BIOS_ERR, "dc: clock init failed\n"); return; } else if (plld_rate != config->pixel_clock * 2) { printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate); config->pixel_clock = plld_rate / 2; } /* Init dc */ if (tegra_dc_init(disp_ctrl)) { printk(BIOS_ERR, "dc: init failed\n"); return; } /* Configure dc mode */ if (update_display_mode(disp_ctrl, config)) { printk(BIOS_ERR, "dc: failed to configure display mode.\n"); return; } /* Enable dp */ dp_enable(dc->out); /* Init frame buffer */ memset((void *)(framebuffer_base_mb*MiB), 0x00, framebuffer_size_mb*MiB); update_window(disp_ctrl, config); /* Set up Tegra PWM n (where n is specified in config->pwm) to drive the * panel backlight. */ printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__); WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) | (220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */ 0x02e), /* frequency divider */ &pwm->pwm[config->pwm].csr); udelay(config->pwm_to_bl_delay_ms * 1000); if (config->backlight_en_gpio){ gpio_output(config->backlight_en_gpio, 1); printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n", __func__, config->backlight_en_gpio, 1); } printk(BIOS_INFO, "%s: display init done.\n", __func__); /* tell depthcharge ... */ struct edid edid; edid.bytes_per_line = ((config->xres * config->framebuffer_bits_per_pixel / 8 + 31) / 32 * 32); edid.x_resolution = edid.bytes_per_line / (config->framebuffer_bits_per_pixel / 8); edid.y_resolution = config->yres; edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); }
int display_init(void *lcdbase, int fb_bits_per_pixel, struct display_timing *timing) { struct dc_ctlr *dc_ctlr; const void *blob = gd->fdt_blob; struct udevice *dp_dev; const int href_to_sync = 1, vref_to_sync = 1; int panel_bpp = 18; /* default 18 bits per pixel */ u32 plld_rate; struct gpio_desc vdd_gpio, enable_gpio; int pwm; int node; int ret; ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev); if (ret) return ret; node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); if (node < 0) return -ENOENT; dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); if (fdtdec_decode_display_timing(blob, node, 0, timing)) return -EINVAL; ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); if (ret) { debug("%s: Failed to decode EDID, using defaults\n", __func__); dump_config(panel_bpp, timing); } if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) { dm_gpio_set_value(&vdd_gpio, 1); debug("%s: backlight vdd setting gpio %08x to %d\n", __func__, gpio_get_number(&vdd_gpio), 1); } /* * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the * update_display_mode() for detail. */ plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); if (plld_rate == 0) { printf("dc: clock init failed\n"); return -EIO; } else if (plld_rate != timing->pixelclock.typ * 2) { debug("dc: plld rounded to %u\n", plld_rate); timing->pixelclock.typ = plld_rate / 2; } /* Init dc */ ret = tegra_dc_init(dc_ctlr); if (ret) { debug("dc: init failed\n"); return ret; } /* Configure dc mode */ ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); if (ret) { debug("dc: failed to configure display mode\n"); return ret; } /* Enable dp */ ret = display_enable(dp_dev, panel_bpp, timing); if (ret) return ret; ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); if (ret) return ret; /* Set up Tegra PWM to drive the panel backlight */ pwm_enable(pwm, 0, 220, 0x2e); udelay(10 * 1000); if (dm_gpio_is_valid(&enable_gpio)) { dm_gpio_set_value(&enable_gpio, 1); debug("%s: backlight enable setting gpio %08x to %d\n", __func__, gpio_get_number(&enable_gpio), 1); } return 0; }
static int display_init(struct udevice *dev, void *lcdbase, int fb_bits_per_pixel, struct display_timing *timing) { struct display_plat *disp_uc_plat; struct dc_ctlr *dc_ctlr; struct udevice *dp_dev; const int href_to_sync = 1, vref_to_sync = 1; int panel_bpp = 18; /* default 18 bits per pixel */ u32 plld_rate; int ret; /* * Before we probe the display device (eDP), tell it that this device * is the source of the display data. */ ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev); if (ret) { debug("%s: device '%s' display not found (ret=%d)\n", __func__, dev->name, ret); return ret; } disp_uc_plat = dev_get_uclass_platdata(dp_dev); debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name, disp_uc_plat); disp_uc_plat->src_dev = dev; ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev); if (ret) { debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret); return ret; } dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev); if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) { debug("%s: Failed to decode display timing\n", __func__); return -EINVAL; } ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); if (ret) { debug("%s: Failed to decode EDID, using defaults\n", __func__); dump_config(panel_bpp, timing); } /* * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the * update_display_mode() for detail. */ plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); if (plld_rate == 0) { printf("dc: clock init failed\n"); return -EIO; } else if (plld_rate != timing->pixelclock.typ * 2) { debug("dc: plld rounded to %u\n", plld_rate); timing->pixelclock.typ = plld_rate / 2; } /* Init dc */ ret = tegra_dc_init(dc_ctlr); if (ret) { debug("dc: init failed\n"); return ret; } /* Configure dc mode */ ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); if (ret) { debug("dc: failed to configure display mode\n"); return ret; } /* Enable dp */ ret = display_enable(dp_dev, panel_bpp, timing); if (ret) { debug("dc: failed to enable display: ret=%d\n", ret); return ret; } ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); if (ret) { debug("dc: failed to update window\n"); return ret; } debug("%s: ready\n", __func__); return 0; }