void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor) { u32 reg_val; struct display_controller *disp_ctrl = (void *)sor->dc->base; tegra_dc_sor_enable_dc(sor); tegra_dc_sor_config_panel(sor, 0); WRITEL(0x9f00, &disp_ctrl->cmd.state_ctrl); WRITEL(0x9f, &disp_ctrl->cmd.state_ctrl); WRITEL(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, &disp_ctrl->cmd.disp_pow_ctrl); reg_val = tegra_sor_readl(sor, NV_SOR_TEST); if (reg_val & NV_SOR_TEST_ATTACHED_TRUE) return; tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_NO); /* * Enable display2sor clock at least 2 cycles before DC start, * to clear sor internal valid signal. */ WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); WRITEL(0, &disp_ctrl->disp.disp_win_opt); WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); /* Attach head */ tegra_dc_sor_update(sor); tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_YES); tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_YES | NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE | NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL); tegra_dc_sor_super_update(sor); /* Enable dc */ reg_val = READL(&disp_ctrl->cmd.state_access); WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); WRITEL(reg_val, &disp_ctrl->cmd.state_access); if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST, NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE, 100, TEGRA_SOR_ATTACH_TIMEOUT_MS * 1000)) printk(BIOS_ERR, "dc timeout waiting for OPMOD = AWAKE\n"); else printk(BIOS_INFO, "%s: sor is attached\n", __func__); #if DEBUG_SOR dump_sor_reg(sor); #endif }
int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev, const struct tegra_dp_link_config *link_cfg, const struct display_timing *timing) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); struct dc_ctlr *disp_ctrl; u32 reg_val; /* Use the first display controller */ debug("%s\n", __func__); disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev); tegra_dc_sor_enable_dc(disp_ctrl); tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); writel(0x9f00, &disp_ctrl->cmd.state_ctrl); writel(0x9f, &disp_ctrl->cmd.state_ctrl); writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, &disp_ctrl->cmd.disp_pow_ctrl); reg_val = tegra_sor_readl(sor, TEST); if (reg_val & TEST_ATTACHED_TRUE) return -EEXIST; tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_NO); /* * Enable display2sor clock at least 2 cycles before DC start, * to clear sor internal valid signal. */ writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); writel(0, &disp_ctrl->disp.disp_win_opt); writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); /* Attach head */ tegra_dc_sor_update(sor); tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_YES); tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_YES | SUPER_STATE1_ASY_HEAD_OP_AWAKE | SUPER_STATE1_ASY_ORMODE_NORMAL); tegra_dc_sor_super_update(sor); /* Enable dc */ reg_val = readl(&disp_ctrl->cmd.state_access); writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd); writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); writel(reg_val, &disp_ctrl->cmd.state_access); if (tegra_dc_sor_poll_register(sor, TEST, TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, TEST_ACT_HEAD_OPMODE_AWAKE, 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) { printf("dc timeout waiting for OPMOD = AWAKE\n"); return -ETIMEDOUT; } else { debug("%s: sor is attached\n", __func__); } #if DEBUG_SOR dump_sor_reg(sor); #endif debug("%s: ret=%d\n", __func__, 0); return 0; }