static char do_decode_rx_error(struct tegra_uart_port *t, u8 lsr)
{
char flag = TTY_NORMAL;
if (unlikely(lsr & UART_LSR_ANY)) {
if (lsr & UART_LSR_OE) {
/* Overrrun error */
flag |= TTY_OVERRUN;
t->uport.icount.overrun++;
dev_err(t->uport.dev, "Got overrun errors\n");
} else if (lsr & UART_LSR_PE) {
/* Parity error */
flag |= TTY_PARITY;
t->uport.icount.parity++;
dev_err(t->uport.dev, "Got Parity errors\n");
} else if (lsr & UART_LSR_FE) {
flag |= TTY_FRAME;
t->uport.icount.frame++;
dev_err(t->uport.dev, "Got frame errors\n");
} else if (lsr & UART_LSR_BI) {
dev_err(t->uport.dev, "Got Break\n");
t->uport.icount.brk++;
/* If FIFO read error without any data, reset Rx FIFO */
if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
tegra_fifo_reset(t, UART_FCR_CLEAR_RCVR);
}
}
return flag;
}
static void tegra_start_rx(struct uart_port *u)
{
struct tegra_uart_port *t;
unsigned char ier;
t = container_of(u, struct tegra_uart_port, uport);
if (t->rts_active)
set_rts(t, true);
if (!t->rx_in_progress) {
wait_sym_time(t, 1); /* wait a character interval */
/* Clear the received Bytes from FIFO */
tegra_fifo_reset(t, UART_FCR_CLEAR_RCVR);
uart_readb(t, UART_LSR);
ier = 0;
ier |= (UART_IER_RLSI | UART_IER_RTOIE);
if (t->use_rx_dma)
ier |= UART_IER_EORD;
else
ier |= UART_IER_RDI;
t->ier_shadow |= ier;
uart_writeb(t, t->ier_shadow, UART_IER);
t->rx_in_progress = 1;
if (t->use_rx_dma && t->rx_dma)
tegra_dma_enqueue_req(t->rx_dma, &t->rx_dma_req);
tty_flip_buffer_push(u->state->port.tty);
}
return;
}
static void tegra_uart_hw_deinit(struct tegra_uart_port *t)
{
unsigned long flags;
unsigned long char_time = DIV_ROUND_UP(10000000, t->baud);
unsigned long fifo_empty_time = t->uport.fifosize * char_time;
unsigned long wait_time;
unsigned char lsr;
unsigned char msr;
unsigned char mcr;
/* Disable interrupts */
uart_writeb(t, 0, UART_IER);
lsr = uart_readb(t, UART_LSR);
if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
msr = uart_readb(t, UART_MSR);
mcr = uart_readb(t, UART_MCR);
if ((mcr & UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
dev_err(t->uport.dev, "%s: Tx fifo not empty and "
"slave disabled CTS, Waiting for slave to"
" be ready\n", __func__);
/* Wait for Tx fifo to be empty */
while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
wait_time = min(fifo_empty_time, 100lu);
udelay(wait_time);
fifo_empty_time -= wait_time;
if (!fifo_empty_time) {
msr = uart_readb(t, UART_MSR);
mcr = uart_readb(t, UART_MCR);
if ((mcr & UART_MCR_CTS_EN) &&
(msr & UART_MSR_CTS))
dev_err(t->uport.dev, "%s: Slave is "
"still not ready!\n", __func__);
break;
}
lsr = uart_readb(t, UART_LSR);
}
}
spin_lock_irqsave(&t->uport.lock, flags);
/* Reset the Rx and Tx FIFOs */
tegra_fifo_reset(t, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
t->baud = 0;
t->uart_state = TEGRA_UART_CLOSED;
spin_unlock_irqrestore(&t->uport.lock, flags);
clk_disable_unprepare(t->clk);
pm_runtime_put_sync((&t->uport)->dev);
}
static void tegra_uart_hw_deinit(struct tegra_uart_port *t)
{
unsigned long flags;
/* Disable interrupts */
uart_writeb(t, 0, UART_IER);
while ((uart_readb(t, UART_LSR) & UART_LSR_TEMT) != UART_LSR_TEMT);
udelay(200);
spin_lock_irqsave(&t->uport.lock, flags);
/* Reset the Rx and Tx FIFOs */
tegra_fifo_reset(t, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
clk_disable(t->clk);
t->baud = 0;
t->uart_state = TEGRA_UART_CLOSED;
spin_unlock_irqrestore(&t->uport.lock, flags);
}
