static int __init ardbeg_fixed_regulator_init(void)
{
struct board_info pmu_board_info;
struct board_info display_board_info;
if ((!of_machine_is_compatible("nvidia,ardbeg")) &&
(!of_machine_is_compatible("nvidia,ardbeg_sata")))
return 0;
tegra_get_display_board_info(&display_board_info);
if (display_board_info.board_id == BOARD_E1824)
platform_add_devices(fixed_reg_devs_e1824,
ARRAY_SIZE(fixed_reg_devs_e1824));
tegra_get_pmu_board_info(&pmu_board_info);
if (pmu_board_info.board_id == BOARD_E1733)
return platform_add_devices(fixed_reg_devs_e1733,
ARRAY_SIZE(fixed_reg_devs_e1733));
else if (pmu_board_info.board_id == BOARD_E1735)
return platform_add_devices(fixed_reg_devs_e1735,
ARRAY_SIZE(fixed_reg_devs_e1735));
else if (pmu_board_info.board_id == BOARD_E1736 ||
pmu_board_info.board_id == BOARD_P1761 ||
pmu_board_info.board_id == BOARD_E1936)
return 0;
else
pr_warn("The PMU board id 0x%04x is not supported\n",
pmu_board_info.board_id);
return 0;
}
static void cardhu_i2c_init(void)
{
struct board_info pmu_board_info;
tegra_get_pmu_board_info(&pmu_board_info);
tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
platform_device_register(&tegra_i2c_device5);
platform_device_register(&tegra_i2c_device4);
platform_device_register(&tegra_i2c_device3);
platform_device_register(&tegra_i2c_device2);
platform_device_register(&tegra_i2c_device1);
i2c_register_board_info(4, cardhu_codec_wm8903_info, 1);
i2c_register_board_info(4, cardhu_codec_max98095_info, 1);
/* Don't register ALC5640 device if there is MAX77663 PMU on system,
* because MAX77663 PMU and ALC5640 Audio Codec are using same i2c addr
* on same i2c bus. */
if (pmu_board_info.board_id != BOARD_PMU_PM298)
i2c_register_board_info(4, cardhu_codec_rt5640_info, 1);
i2c_register_board_info(4, cardhu_codec_aic326x_info, 1);
i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
}
int __init cardhu_pm298_regulator_init(void)
{
struct board_info board_info;
struct board_info pmu_board_info;
void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
u32 pmc_ctrl;
/* configure the power management controller to trigger PMU
* interrupts when low */
pmc_ctrl = readl(pmc + PMC_CTRL);
writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
/* The regulator details have complete constraints */
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
if (pmu_board_info.board_id != BOARD_PMU_PM298) {
pr_err("%s(): Board ID is not proper\n", __func__);
return -ENODEV;
}
i2c_register_board_info(4, max77663_regulators,
ARRAY_SIZE(max77663_regulators));
return 0;
}
static void __init tegra_cardhu_init(void)
{
struct board_info pmu_board_info;
tegra_get_pmu_board_info(&pmu_board_info);
tegra_thermal_init(&thermal_data);
tegra_clk_init_from_table(cardhu_clk_init_table);
cardhu_pinmux_init();
cardhu_misc_init();
tegra_booting_info( );
cardhu_i2c_init();
cardhu_spi_init();
cardhu_usb_init();
#ifdef CONFIG_TEGRA_EDP_LIMITS
cardhu_edp_init();
#endif
cardhu_uart_init();
snprintf(cardhu_chipid, sizeof(cardhu_chipid), "%016llx",
tegra_chip_uid());
cardhu_tsensor_init();
platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
/* Don't register ALC5640 device if there is MAX77663 PMU on system,
* because MAX77663 PMU and ALC5640 Audio Codec are using same i2c addr
* on same i2c bus. */
if (pmu_board_info.board_id != BOARD_PMU_PM298)
platform_device_register(&cardhu_audio_rt5640_device);
tegra_ram_console_debug_init();
cardhu_sdhci_init();
cardhu_regulator_init();
cardhu_dtv_init();
cardhu_suspend_init();
cardhu_power_off_init();
cardhu_touch_init();
cardhu_gps_init();
cardhu_modem_init();
cardhu_kbc_init();
cardhu_scroll_init();
cardhu_keys_init();
cardhu_panel_init();
cardhu_pmon_init();
cardhu_sensors_init();
cardhu_setup_bluesleep();
cardhu_sata_init();
//audio_wired_jack_init();
cardhu_pins_state_init();
cardhu_emc_init();
tegra_release_bootloader_fb();
cardhu_nfc_init();
cardhu_pci_init();
#ifdef CONFIG_TEGRA_WDT_RECOVERY
tegra_wdt_recovery_init();
#endif
}
int __init cardhu_power_off_init(void)
{
struct board_info pmu_board_info;
tegra_get_pmu_board_info(&pmu_board_info);
pm_power_off = cardhu_power_off;
return 0;
}
int __init cardhu_power_off_init(void)
{
struct board_info pmu_board_info;
tegra_get_pmu_board_info(&pmu_board_info);
if (pmu_board_info.board_id == BOARD_PMU_PM298)
pm_power_off = cardhu_pm298_power_off;
else
pm_power_off = cardhu_power_off;
return 0;
}
int __init ardbeg_rail_alignment_init(void)
{
struct board_info pmu_board_info;
tegra_get_pmu_board_info(&pmu_board_info);
#ifdef CONFIG_ARCH_TEGRA_13x_SOC
#else
if (pmu_board_info.board_id == BOARD_E1735)
tegra12x_vdd_cpu_align(E1735_CPU_VDD_STEP_UV,
E1735_CPU_VDD_MIN_UV);
else
tegra12x_vdd_cpu_align(ARDBEG_DEFAULT_CVB_ALIGNMENT, 0);
#endif
return 0;
}
int __init cardhu_suspend_init(void)
{
struct board_info board_info;
struct board_info pmu_board_info;
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
/* For PMU Fab A03, A04 and A05 make core_pwr_req to high */
if ((pmu_board_info.fab == BOARD_FAB_A03) ||
(pmu_board_info.fab == BOARD_FAB_A04) ||
(pmu_board_info.fab == BOARD_FAB_A05))
cardhu_suspend_data.corereq_high = true;
/* CORE_PWR_REQ to be high for all processor/pmu board whose sku bit 0
* is set. This is require to enable the dc-dc converter tps62361x */
if ((board_info.sku & SKU_DCDC_TPS62361_SUPPORT) || (pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT))
cardhu_suspend_data.corereq_high = true;
switch (board_info.board_id) {
case BOARD_E1291:
/* CORE_PWR_REQ to be high for E1291-A03 */
if (board_info.fab == BOARD_FAB_A03)
cardhu_suspend_data.corereq_high = true;
break;
case BOARD_E1198:
case BOARD_PM269:
case BOARD_PM305:
case BOARD_PM311:
break;
case BOARD_E1187:
case BOARD_E1186:
case BOARD_E1256:
case BOARD_E1257:
cardhu_suspend_data.cpu_timer = 5000;
cardhu_suspend_data.cpu_off_timer = 5000;
break;
default:
break;
}
tegra_init_suspend(&cardhu_suspend_data);
return 0;
}
int __init cardhu_pm299_regulator_init(void)
{
struct board_info board_info;
struct board_info pmu_board_info;
void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
u32 pmc_ctrl;
/* configure the power management controller to trigger PMU
* interrupts when low */
pmc_ctrl = readl(pmc + PMC_CTRL);
writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
/* The regulator details have complete constraints */
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
if (pmu_board_info.board_id != BOARD_PMU_PM299) {
pr_err("%s(): Board ID is not proper\n", __func__);
return -ENODEV;
}
/* If TPS6236x DCDC is there then consumer for dc1 should
* not have vdd_core */
if ((board_info.sku & SKU_DCDC_TPS62361_SUPPORT) ||
(pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT)) {
pdata_dc1_skubit0_0.regulator.consumer_supplies =
ricoh583_dc1_supply_skubit0_1;
pdata_dc1_skubit0_0.regulator.num_consumer_supplies =
ARRAY_SIZE(ricoh583_dc1_supply_skubit0_1);
}
ricoh_platform.num_subdevs = ARRAY_SIZE(ricoh_devs_e118x_dcdc);
ricoh_platform.subdevs = ricoh_devs_e118x_dcdc;
i2c_register_board_info(4, ricoh583_regulators, 1);
/* Register the TPS6236x for all boards whose sku bit 0 is set. */
if ((board_info.sku & SKU_DCDC_TPS62361_SUPPORT) ||
(pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT)) {
pr_info("Registering the device TPS62361\n");
i2c_register_board_info(4, tps62361_boardinfo, 1);
}
return 0;
}
static void ardbeg_modem_init(void)
{
int modem_id = tegra_get_modem_id();
struct board_info board_info;
struct board_info pmu_board_info;
int usb_port_owner_info = tegra_get_usb_port_owner_info();
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
pr_info("%s: modem_id = %d\n", __func__, modem_id);
switch (modem_id) {
case TEGRA_BB_BRUCE:
if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
/* Set specific USB wake source for Ardbeg */
if (board_info.board_id == BOARD_E1780)
tegra_set_wake_source(42, INT_USB2);
if (pmu_board_info.board_id == BOARD_E1736 ||
pmu_board_info.board_id == BOARD_E1769 ||
pmu_board_info.board_id == BOARD_E1936)
baseband_pdata.regulator_name = NULL;
platform_device_register(&icera_bruce_device);
}
break;
case TEGRA_BB_HSIC_HUB: /* HSIC hub */
if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
tegra_ehci2_device.dev.platform_data =
&tegra_ehci2_hsic_smsc_hub_pdata;
/* Set specific USB wake source for Ardbeg */
if (board_info.board_id == BOARD_E1780)
tegra_set_wake_source(42, INT_USB2);
platform_device_register(&tegra_ehci2_device);
} else
xusb_pdata.pretend_connect_0 = true;
break;
default:
return;
}
}
int __init cardhu_regulator_init(void)
{
struct board_info board_info;
struct board_info pmu_board_info;
void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
u32 pmc_ctrl;
/* configure the power management controller to trigger PMU
* interrupts when low */
pmc_ctrl = readl(pmc + PMC_CTRL);
writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
/* The regulator details have complete constraints */
regulator_has_full_constraints();
tps_platform.num_subdevs = ARRAY_SIZE(tps_devs_picasso2);
tps_platform.subdevs = tps_devs_picasso2;
i2c_register_board_info(4, cardhu_regulators, 1);
pr_info("Registering the device TPS62361B\n");
i2c_register_board_info(4, tps6236x_boardinfo, 1);
tps_platform.dev_slp_en = true;
tps_platform.gpio_init_data = tps_gpio_pdata_e1291_a04;
tps_platform.num_gpioinit_data = ARRAY_SIZE(tps_gpio_pdata_e1291_a04);
#ifdef CONFIG_BATTERY_BQ27541
bq27541_gpio_init();
i2c_register_board_info(4, bq27541_boardinfo, 1);
#endif
return 0;
}
int __init ardbeg_regulator_init(void)
{
struct board_info pmu_board_info;
tegra_get_pmu_board_info(&pmu_board_info);
if ((pmu_board_info.board_id == BOARD_E1733) ||
(pmu_board_info.board_id == BOARD_E1734)) {
i2c_register_board_info(0, tca6408_expander,
ARRAY_SIZE(tca6408_expander));
ardbeg_ams_regulator_init();
regulator_has_full_constraints();
} else if (pmu_board_info.board_id == BOARD_E1735) {
regulator_has_full_constraints();
ardbeg_tps65913_regulator_init();
#ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
tegra_init_cpu_reg_mode_limits(
E1735_CPU_VDD_IDLE_MA, REGULATOR_MODE_IDLE);
#endif
} else if (pmu_board_info.board_id == BOARD_E1736 ||
pmu_board_info.board_id == BOARD_E1936 ||
pmu_board_info.board_id == BOARD_E1769 ||
pmu_board_info.board_id == BOARD_P1761) {
tn8_regulator_init();
return tn8_fixed_regulator_init();
} else {
pr_warn("PMU board id 0x%04x is not supported\n",
pmu_board_info.board_id);
}
if (pmu_board_info.board_id != BOARD_E1735)
platform_device_register(&power_supply_extcon_device);
ardbeg_cl_dvfs_init(&pmu_board_info);
return 0;
}
int __init ardbeg_suspend_init(void)
{
struct board_info pmu_board_info;
tegra_get_pmu_board_info(&pmu_board_info);
if (pmu_board_info.board_id == BOARD_E1735) {
struct tegra_suspend_platform_data *data = &ardbeg_suspend_data;
if (pmu_board_info.sku != E1735_EMULATE_E1767_SKU) {
data->cpu_timer = 2000;
data->crail_up_early = true;
#ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
data->suspend_dfll_bypass = e1735_suspend_dfll_bypass;
data->resume_dfll_bypass = e1735_resume_dfll_bypass;
} else {
data->suspend_dfll_bypass = e1767_suspend_dfll_bypass;
data->resume_dfll_bypass = e1767_resume_dfll_bypass;
#endif
}
}
tegra_init_suspend(&ardbeg_suspend_data);
return 0;
}
int __init norrin_soctherm_init(void)
{
const int t13x_cpu_edp_temp_margin = 5000,
t13x_gpu_edp_temp_margin = 6000;
int cp_rev, ft_rev;
struct board_info pmu_board_info;
struct board_info board_info;
enum soctherm_therm_id therm_cpu = THERM_CPU;
tegra_get_board_info(&board_info);
cp_rev = tegra_fuse_calib_base_get_cp(NULL, NULL);
ft_rev = tegra_fuse_calib_base_get_ft(NULL, NULL);
if (cp_rev) {
/* ATE rev is Old or Mid - use PLLx sensor only */
norrin_soctherm_data.therm[THERM_CPU] =
norrin_v1_soctherm_data.therm[THERM_CPU];
norrin_soctherm_data.therm[THERM_PLL] =
norrin_v1_soctherm_data.therm[THERM_PLL];
therm_cpu = THERM_PLL; /* override CPU with PLL zone */
}
/* do this only for supported CP,FT fuses */
if ((cp_rev >= 0) && (ft_rev >= 0)) {
tegra_platform_edp_init(
norrin_soctherm_data.therm[therm_cpu].trips,
&norrin_soctherm_data.therm[therm_cpu].num_trips,
t13x_cpu_edp_temp_margin);
tegra_platform_gpu_edp_init(
norrin_soctherm_data.therm[THERM_GPU].trips,
&norrin_soctherm_data.therm[THERM_GPU].num_trips,
t13x_gpu_edp_temp_margin);
tegra_add_cpu_vmax_trips(
norrin_soctherm_data.therm[therm_cpu].trips,
&norrin_soctherm_data.therm[therm_cpu].num_trips);
tegra_add_tgpu_trips(
norrin_soctherm_data.therm[THERM_GPU].trips,
&norrin_soctherm_data.therm[THERM_GPU].num_trips);
tegra_add_core_vmax_trips(
norrin_soctherm_data.therm[THERM_PLL].trips,
&norrin_soctherm_data.therm[THERM_PLL].num_trips);
}
if (board_info.board_id == BOARD_PM374 ||
board_info.board_id == BOARD_PM375 ||
board_info.board_id == BOARD_E1971 ||
board_info.board_id == BOARD_E1991) {
tegra_add_cpu_vmin_trips(
norrin_soctherm_data.therm[therm_cpu].trips,
&norrin_soctherm_data.therm[therm_cpu].num_trips);
tegra_add_gpu_vmin_trips(
norrin_soctherm_data.therm[THERM_GPU].trips,
&norrin_soctherm_data.therm[THERM_GPU].num_trips);
tegra_add_core_vmin_trips(
norrin_soctherm_data.therm[THERM_PLL].trips,
&norrin_soctherm_data.therm[THERM_PLL].num_trips);
}
if (board_info.board_id == BOARD_PM375)
tegra_add_cpu_clk_switch_trips(
norrin_soctherm_data.therm[THERM_CPU].trips,
&norrin_soctherm_data.therm[THERM_CPU].num_trips);
tegra_get_pmu_board_info(&pmu_board_info);
if ((pmu_board_info.board_id == BOARD_PM374) ||
(pmu_board_info.board_id == BOARD_PM375))
norrin_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
else
pr_warn("soctherm THERMTRIP not supported on PMU (BOARD_P%d)\n",
pmu_board_info.board_id);
return tegra11_soctherm_init(&norrin_soctherm_data);
}
int __init cardhu_regulator_init(void)
{
struct board_info board_info;
struct board_info pmu_board_info;
void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
u32 pmc_ctrl;
/* configure the power management controller to trigger PMU
* interrupts when low */
pmc_ctrl = readl(pmc + PMC_CTRL);
writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
if (pmu_board_info.board_id == BOARD_PMU_PM298)
return cardhu_pm298_regulator_init();
if (pmu_board_info.board_id == BOARD_PMU_PM299)
return cardhu_pm299_regulator_init();
/* The regulator details have complete constraints */
regulator_has_full_constraints();
/* PMU-E1208, the ldo2 should be set to 1200mV */
if (pmu_board_info.board_id == BOARD_E1208) {
pdata_ldo2_0.regulator.constraints.min_uV = 1200000;
pdata_ldo2_0.regulator.constraints.max_uV = 1200000;
}
if ((board_info.board_id == BOARD_E1198) ||
(board_info.board_id == BOARD_E1291)) {
if (board_info.sku & SKU_DCDC_TPS62361_SUPPORT) {
tps_platform.num_subdevs =
ARRAY_SIZE(tps_devs_e1198_skubit0_1);
tps_platform.subdevs = tps_devs_e1198_skubit0_1;
} else {
tps_platform.num_subdevs =
ARRAY_SIZE(tps_devs_e1198_skubit0_0);
tps_platform.subdevs = tps_devs_e1198_skubit0_0;
}
} else {
if (board_info.board_id == BOARD_PM269)
pdata_ldo3_e118x.slew_rate_uV_per_us = 250;
if (pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT) {
tps_platform.num_subdevs = ARRAY_SIZE(tps_devs_e118x_skubit0_1);
tps_platform.subdevs = tps_devs_e118x_skubit0_1;
} else {
tps_platform.num_subdevs = ARRAY_SIZE(tps_devs_e118x_skubit0_0);
tps_platform.subdevs = tps_devs_e118x_skubit0_0;
}
}
/* E1291-A04/A05: Enable DEV_SLP and enable sleep on GPIO2 */
if ((board_info.board_id == BOARD_E1291) &&
((board_info.fab == BOARD_FAB_A04) ||
(board_info.fab == BOARD_FAB_A05))) {
tps_platform.dev_slp_en = true;
tps_platform.gpio_init_data = tps_gpio_pdata_e1291_a04;
tps_platform.num_gpioinit_data =
ARRAY_SIZE(tps_gpio_pdata_e1291_a04);
}
i2c_register_board_info(4, cardhu_regulators, 1);
/* Resgister the TPS6236x for all boards whose sku bit 0 is set. */
if ((board_info.sku & SKU_DCDC_TPS62361_SUPPORT) ||
(pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT)) {
pr_info("Registering the device TPS62361B\n");
i2c_register_board_info(4, tps6236x_boardinfo, 1);
}
is_cardhu_machine = true;
return 0;
}
int __init ardbeg_soctherm_init(void)
{
s32 base_cp, shft_cp;
u32 base_ft, shft_ft;
struct board_info pmu_board_info;
struct board_info board_info;
tegra_get_board_info(&board_info);
if (board_info.board_id == BOARD_E1923 ||
board_info.board_id == BOARD_E1922) {
memcpy(ardbeg_soctherm_data.therm,
ardbeg_therm_pop, sizeof(ardbeg_therm_pop));
}
/* do this only for supported CP,FT fuses */
if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
(tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
tegra_platform_edp_init(
ardbeg_soctherm_data.therm[THERM_CPU].trips,
&ardbeg_soctherm_data.therm[THERM_CPU].num_trips,
7000); /* edp temperature margin */
tegra_platform_gpu_edp_init(
ardbeg_soctherm_data.therm[THERM_GPU].trips,
&ardbeg_soctherm_data.therm[THERM_GPU].num_trips,
7000);
tegra_add_cpu_vmax_trips(
ardbeg_soctherm_data.therm[THERM_CPU].trips,
&ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
tegra_add_tgpu_trips(
ardbeg_soctherm_data.therm[THERM_GPU].trips,
&ardbeg_soctherm_data.therm[THERM_GPU].num_trips);
tegra_add_vc_trips(
ardbeg_soctherm_data.therm[THERM_CPU].trips,
&ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
tegra_add_core_vmax_trips(
ardbeg_soctherm_data.therm[THERM_PLL].trips,
&ardbeg_soctherm_data.therm[THERM_PLL].num_trips);
}
if (board_info.board_id == BOARD_P1761 ||
board_info.board_id == BOARD_E1784 ||
board_info.board_id == BOARD_E1971 ||
board_info.board_id == BOARD_E1991 ||
board_info.board_id == BOARD_E1922) {
tegra_add_cpu_vmin_trips(
ardbeg_soctherm_data.therm[THERM_CPU].trips,
&ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
tegra_add_gpu_vmin_trips(
ardbeg_soctherm_data.therm[THERM_GPU].trips,
&ardbeg_soctherm_data.therm[THERM_GPU].num_trips);
tegra_add_core_vmin_trips(
ardbeg_soctherm_data.therm[THERM_PLL].trips,
&ardbeg_soctherm_data.therm[THERM_PLL].num_trips);
}
tegra_get_pmu_board_info(&pmu_board_info);
if ((pmu_board_info.board_id == BOARD_E1733) ||
(pmu_board_info.board_id == BOARD_E1734))
ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
else if (pmu_board_info.board_id == BOARD_E1735 ||
pmu_board_info.board_id == BOARD_E1736 ||
pmu_board_info.board_id == BOARD_E1769 ||
pmu_board_info.board_id == BOARD_P1761 ||
pmu_board_info.board_id == BOARD_E1936)
ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_palmas;
else
pr_warn("soctherm THERMTRIP not supported on PMU (BOARD_E%d)\n",
pmu_board_info.board_id);
/* Enable soc_therm OC throttling on selected platforms */
switch (pmu_board_info.board_id) {
case BOARD_P1761:
memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC4],
&battery_oc_throttle,
sizeof(battery_oc_throttle));
memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC1],
&voltmon_throttle,
sizeof(voltmon_throttle));
break;
default:
break;
}
return tegra11_soctherm_init(&ardbeg_soctherm_data);
}
static void ardbeg_usb_init(void)
{
int usb_port_owner_info = tegra_get_usb_port_owner_info();
int modem_id = tegra_get_modem_id();
struct board_info bi;
tegra_get_pmu_board_info(&bi);
if (board_info.sku == 1100 || board_info.board_id == BOARD_P1761 ||
board_info.board_id == BOARD_E1784)
tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
if (board_info.board_id == BOARD_PM359 ||
board_info.board_id == BOARD_PM358 ||
board_info.board_id == BOARD_PM370 ||
board_info.board_id == BOARD_PM374 ||
board_info.board_id == BOARD_PM363) {
/* Laguna */
/* Host cable is detected through AMS PMU Interrupt */
tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
tegra_ehci1_utmi_pdata.id_extcon_dev_name = "as3722-extcon";
} else {
/* Ardbeg and TN8 */
/* Need these settings for HS USB EMI on T124 */
tegra_udc_pdata.u_cfg.utmi.xcvr_hsslew_lsb = 0x3;
tegra_udc_pdata.u_cfg.utmi.xcvr_hsslew_msb = 0xf;
tegra_ehci1_utmi_pdata.u_cfg.utmi.xcvr_hsslew_lsb = 0x3;
tegra_ehci1_utmi_pdata.u_cfg.utmi.xcvr_hsslew_msb = 0xf;
tegra_ehci2_utmi_pdata.u_cfg.utmi.xcvr_hsslew_lsb = 0x3;
tegra_ehci2_utmi_pdata.u_cfg.utmi.xcvr_hsslew_msb = 0xf;
tegra_ehci3_utmi_pdata.u_cfg.utmi.xcvr_hsslew_lsb = 0x3;
tegra_ehci3_utmi_pdata.u_cfg.utmi.xcvr_hsslew_msb = 0xf;
/*
* TN8 supports vbus changing and it can handle
* vbus voltages larger then 5V. Enable this.
*/
if (board_info.board_id == BOARD_P1761 ||
board_info.board_id == BOARD_E1784 ||
board_info.board_id == BOARD_E1780) {
/*
* Set the maximum voltage that can be supplied
* over USB vbus that the board supports if we use
* a quick charge 2 wall charger.
*/
tegra_udc_pdata.qc2_voltage = TEGRA_USB_QC2_12V;
tegra_udc_pdata.u_data.dev.qc2_current_limit_ma = 1300;
/* charger needs to be set to 3A - h/w will do 2A */
tegra_udc_pdata.u_data.dev.dcp_current_limit_ma = 3000;
}
switch (bi.board_id) {
case BOARD_E1733:
/* Host cable is detected through PMU Interrupt */
tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
tegra_ehci1_utmi_pdata.id_extcon_dev_name =
"as3722-extcon";
break;
case BOARD_E1736:
case BOARD_E1769:
case BOARD_E1735:
case BOARD_E1936:
case BOARD_P1761:
/* Device cable is detected through PMU Interrupt */
tegra_udc_pdata.support_pmu_vbus = true;
tegra_udc_pdata.vbus_extcon_dev_name = "palmas-extcon";
tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
tegra_ehci1_utmi_pdata.vbus_extcon_dev_name =
"palmas-extcon";
/* Host cable is detected through PMU Interrupt */
tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
tegra_ehci1_utmi_pdata.id_extcon_dev_name =
"palmas-extcon";
}
/* Enable Y-Cable support */
if (bi.board_id == BOARD_P1761)
tegra_ehci1_utmi_pdata.u_data.host.support_y_cable =
true;
}
if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
tegra_otg_pdata.is_xhci = false;
tegra_udc_pdata.u_data.dev.is_xhci = false;
} else {
tegra_otg_pdata.is_xhci = true;
tegra_udc_pdata.u_data.dev.is_xhci = true;
}
tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
platform_device_register(&tegra_otg_device);
/* Setup the udc platform data */
tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
if (!modem_id) {
if ((bi.board_id != BOARD_P1761) &&
(bi.board_id != BOARD_E1922) &&
(bi.board_id != BOARD_E1784)) {
tegra_ehci2_device.dev.platform_data =
&tegra_ehci2_utmi_pdata;
platform_device_register(&tegra_ehci2_device);
}
}
}
if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
if ((bi.board_id != BOARD_P1761) &&
(bi.board_id != BOARD_E1922) &&
(bi.board_id != BOARD_E1784)) {
tegra_ehci3_device.dev.platform_data =
&tegra_ehci3_utmi_pdata;
platform_device_register(&tegra_ehci3_device);
}
}
}
int __init cardhu_fixed_regulator_init(void)
{
int i;
struct board_info board_info;
struct board_info pmu_board_info;
struct board_info display_board_info;
struct platform_device **fixed_reg_devs;
int nfixreg_devs;
if (!is_cardhu_machine)
return 0;
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
tegra_get_display_board_info(&display_board_info);
if (pmu_board_info.board_id == BOARD_PMU_PM298)
return cardhu_pm298_gpio_switch_regulator_init();
if (pmu_board_info.board_id == BOARD_PMU_PM299)
return cardhu_pm299_gpio_switch_regulator_init();
switch (board_info.board_id) {
case BOARD_E1198:
if (board_info.fab <= BOARD_FAB_A01) {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1198_base);
fixed_reg_devs = fixed_reg_devs_e1198_base;
} else {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1198_a02);
fixed_reg_devs = fixed_reg_devs_e1198_a02;
}
break;
case BOARD_E1291:
if (board_info.fab == BOARD_FAB_A03) {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1291_a03);
fixed_reg_devs = fixed_reg_devs_e1291_a03;
} else if ((board_info.fab == BOARD_FAB_A04) ||
(board_info.fab == BOARD_FAB_A05)) {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1291_a04);
fixed_reg_devs = fixed_reg_devs_e1291_a04;
} else {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1198_base);
fixed_reg_devs = fixed_reg_devs_e1198_base;
}
break;
case BOARD_PM311:
case BOARD_PM305:
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm311);
fixed_reg_devs = fixed_reg_devs_pm311;
if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm311_pm313);
fixed_reg_devs = fixed_reg_devs_pm311_pm313;
}
break;
case BOARD_PM269:
case BOARD_E1257:
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm269);
fixed_reg_devs = fixed_reg_devs_pm269;
if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm269_pm313);
fixed_reg_devs = fixed_reg_devs_pm269_pm313;
} else {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm269);
fixed_reg_devs = fixed_reg_devs_pm269;
}
break;
default:
if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e118x_pm313);
fixed_reg_devs = fixed_reg_devs_e118x_pm313;
} else {
nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e118x);
fixed_reg_devs = fixed_reg_devs_e118x;
}
break;
}
for (i = 0; i < nfixreg_devs; ++i) {
int gpio_nr;
if (!strncmp(fixed_reg_devs[i]->name, "gpio", 4)) {
struct gpio_switch_regulator_platform_data *gs_pdata =
fixed_reg_devs[i]->dev.platform_data;
gpio_nr = gs_pdata->subdevs[0]->gpio_nr;
} else {
struct fixed_voltage_config *fixed_reg_pdata =
fixed_reg_devs[i]->dev.platform_data;
gpio_nr = fixed_reg_pdata->gpio;
}
if (gpio_nr < TEGRA_NR_GPIOS)
tegra_gpio_enable(gpio_nr);
}
return platform_add_devices(fixed_reg_devs, nfixreg_devs);
}
int __init cardhu_keys_init(void)
{
int i;
struct board_info board_info;
struct board_info pmu_board_info;
int gpio_nr;
tegra_get_board_info(&board_info);
if (!((board_info.board_id == BOARD_E1198) ||
(board_info.board_id == BOARD_E1291) ||
(board_info.board_id == BOARD_PM315) ||
(board_info.board_id == BOARD_E1186) ||
(board_info.board_id == BOARD_E1257) ||
(board_info.board_id == BOARD_PM305) ||
(board_info.board_id == BOARD_PM311) ||
(board_info.board_id == BOARD_PM267) ||
(board_info.board_id == BOARD_PM269)))
return 0;
pr_info("Registering gpio keys\n");
if (board_info.board_id == BOARD_E1291) {
if (board_info.fab >= BOARD_FAB_A04) {
cardhu_keys_e1291_pdata.buttons =
cardhu_keys_e1291_a04;
cardhu_keys_e1291_pdata.nbuttons =
ARRAY_SIZE(cardhu_keys_e1291_a04);
}
/* Enable gpio mode for other pins */
for (i = 0; i < cardhu_keys_e1291_pdata.nbuttons; i++) {
gpio_nr = cardhu_keys_e1291_pdata.buttons[i].gpio;
if (gpio_nr < 0) {
if (get_tegra_image_type() == rck_image)
cardhu_keys_e1291_pdata.buttons[i].code
= KEY_ENTER;
}
}
platform_device_register(&cardhu_keys_e1291_device);
} else if (board_info.board_id == BOARD_E1198) {
/* For E1198 */
for (i = 0; i < ARRAY_SIZE(cardhu_keys_e1198); i++) {
gpio_nr = cardhu_keys_e1198[i].gpio;
if (gpio_nr < 0) {
if (get_tegra_image_type() == rck_image)
cardhu_keys_e1198[i].code = KEY_ENTER;
}
}
platform_device_register(&cardhu_keys_e1198_device);
}
/* Register on-key through pmu interrupt */
tegra_get_pmu_board_info(&pmu_board_info);
if (pmu_board_info.board_id == BOARD_PMU_PM298) {
cardhu_int_keys_pdata.buttons = cardhu_pm298_int_keys;
cardhu_int_keys_pdata.nbuttons =
ARRAY_SIZE(cardhu_pm298_int_keys);
}
if (pmu_board_info.board_id == BOARD_PMU_PM299) {
cardhu_int_keys_pdata.buttons = cardhu_pm299_int_keys;
cardhu_int_keys_pdata.nbuttons =
ARRAY_SIZE(cardhu_pm299_int_keys);
}
if ((board_info.board_id == BOARD_E1257) ||
(board_info.board_id == BOARD_E1186) ||
(board_info.board_id == BOARD_PM305) ||
(board_info.board_id == BOARD_PM315) ||
(board_info.board_id == BOARD_PM311) ||
(board_info.board_id == BOARD_PM267) ||
(board_info.board_id == BOARD_PM269)) {
if (get_tegra_image_type() == rck_image)
cardhu_int_keys[0].code = KEY_ENTER;
platform_device_register(&cardhu_int_keys_device);
}
return 0;
}
int __init cardhu_gpio_switch_regulator_init(void)
{
int i;
struct board_info board_info;
struct board_info pmu_board_info;
struct board_info display_board_info;
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
tegra_get_display_board_info(&display_board_info);
if (pmu_board_info.board_id == BOARD_PMU_PM299)
return cardhu_pm299_gpio_switch_regulator_init();
switch (board_info.board_id) {
case BOARD_E1198:
if (board_info.fab <= BOARD_FAB_A01) {
gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_e1198_base);
gswitch_pdata.subdevs = gswitch_subdevs_e1198_base;
} else {
gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_e1198_a02);
gswitch_pdata.subdevs = gswitch_subdevs_e1198_a02;
}
break;
case BOARD_E1291:
if (board_info.fab == BOARD_FAB_A03) {
gswitch_pdata.num_subdevs =
ARRAY_SIZE(gswitch_subdevs_e1291_a03);
gswitch_pdata.subdevs = gswitch_subdevs_e1291_a03;
} else if (board_info.fab == BOARD_FAB_A04) {
gswitch_pdata.num_subdevs =
ARRAY_SIZE(gswitch_subdevs_e1291_a04);
gswitch_pdata.subdevs = gswitch_subdevs_e1291_a04;
} else {
gswitch_pdata.num_subdevs =
ARRAY_SIZE(gswitch_subdevs_e1198_base);
gswitch_pdata.subdevs = gswitch_subdevs_e1198_base;
}
break;
case BOARD_PM269:
//case BOARD_PM305:
//case BOARD_PM311:
//case BOARD_E1257:
gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_pm269);
gswitch_pdata.subdevs = gswitch_subdevs_pm269;
if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_pm269_pm313);
gswitch_pdata.subdevs = gswitch_subdevs_pm269_pm313;
} else {
gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_pm269);
gswitch_pdata.subdevs = gswitch_subdevs_pm269;
}
break;
default:
if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_e118x_pm313);
gswitch_pdata.subdevs = gswitch_subdevs_e118x_pm313;
} else {
gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_e118x);
gswitch_pdata.subdevs = gswitch_subdevs_e118x;
}
break;
}
for (i = 0; i < gswitch_pdata.num_subdevs; ++i) {
struct gpio_switch_regulator_subdev_data *gswitch_data = gswitch_pdata.subdevs[i];
if (gswitch_data->gpio_nr <= TEGRA_NR_GPIOS)
tegra_gpio_enable(gswitch_data->gpio_nr);
}
return platform_device_register(&gswitch_regulator_pdata);
}