void tegra_fiq_disable(int irq) { #if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \ defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) tegra_legacy_avp_irq_unmask(irq); #else tegra_fiq_mask(irq_get_irq_data(irq)); tegra_legacy_select_fiq(irq, false); #endif }
void tegra_fiq_enable(int irq) { void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100); /* enable FIQ */ u32 val = readl(base + GIC_CPU_CTRL); val &= ~8; /* pass FIQs through */ val |= 2; /* enableNS */ writel(val, base + GIC_CPU_CTRL); tegra_legacy_select_fiq(irq, true); tegra_legacy_unmask_irq(irq); }
void tegra_fiq_enable(int irq) { #if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \ defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) tegra_legacy_avp_irq_mask(irq); #else void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100); /* enable FIQ */ u32 val = readl(base + GIC_CPU_CTRL); val &= ~8; /* pass FIQs through */ val |= 2; /* enableNS */ writel(val, base + GIC_CPU_CTRL); tegra_legacy_select_fiq(irq, true); tegra_fiq_unmask(irq_get_irq_data(irq)); #endif }
void tegra_fiq_disable(int irq) { tegra_legacy_mask_irq(irq); tegra_legacy_select_fiq(irq, false); }
void tegra_fiq_disable(int irq) { tegra_fiq_mask(irq_get_irq_data(irq)); tegra_legacy_select_fiq(irq, false); }