static void __init tegra_init_power(void)
{
tegra_powergate_power_off(TEGRA_POWERGATE_MPE);
#if !CONFIG_DISABLE_3D_POWERGATING
tegra_powergate_power_off(TEGRA_POWERGATE_3D);
#endif
tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
}
static void powerdown_handler(struct work_struct *work)
{
struct nvhost_module *mod;
int refcount;
mod = container_of(to_delayed_work(work), struct nvhost_module, powerdown);
mutex_lock(&mod->lock);
refcount = atomic_read(&mod->refcount);
if ((refcount == 0) && mod->powered) {
int i;
if (mod->func)
mod->func(mod, NVHOST_POWER_ACTION_OFF);
for (i = 0; i < mod->num_clks; i++) {
clk_disable(mod->clk[i]);
}
if (mod->powergate_id != -1) {
tegra_periph_reset_assert(mod->clk[0]);
tegra_powergate_power_off(mod->powergate_id);
}
mod->powered = false;
if (mod->parent)
nvhost_module_idle(mod->parent);
}
else if (mod->force_suspend) {
pr_warn("tegra_grhost: module %s (refcnt %d)"
" force_suspend powerdown skipped!\n",
mod->name, refcount);
}
mod->force_suspend = false;
mutex_unlock(&mod->lock);
}
/* Must be called with clk disabled, and returns with clk enabled */
int tegra_powergate_sequence_power_up(int id, struct clk *clk,
struct reset_control *rst)
{
int ret;
reset_control_assert(rst);
ret = tegra_powergate_power_on(id);
if (ret)
goto err_power;
ret = clk_prepare_enable(clk);
if (ret)
goto err_clk;
udelay(10);
ret = tegra_powergate_remove_clamping(id);
if (ret)
goto err_clamp;
udelay(10);
reset_control_deassert(rst);
return 0;
err_clamp:
clk_disable_unprepare(clk);
err_clk:
tegra_powergate_power_off(id);
err_power:
return ret;
}
/* Must be called with clk disabled, and returns with clk enabled */
int tegra_powergate_sequence_power_up(int id, struct clk *clk)
{
int ret;
tegra_periph_reset_assert(clk);
ret = tegra_powergate_power_on(id);
if (ret)
goto err_power;
ret = clk_enable(clk);
if (ret)
goto err_clk;
udelay(10);
ret = tegra_powergate_remove_clamping(id);
if (ret)
goto err_clamp;
udelay(10);
tegra_periph_reset_deassert(clk);
return 0;
err_clamp:
clk_disable(clk);
err_clk:
tegra_powergate_power_off(id);
err_power:
return ret;
}
int
tegra_powergate_sequence_power_up(enum tegra_powergate_id id, clk_t clk,
hwreset_t rst)
{
struct tegra124_pmc_softc *sc;
int rv;
sc = tegra124_pmc_get_sc();
rv = hwreset_assert(rst);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert reset\n");
return (rv);
}
rv = clk_stop(clk);
if (rv != 0) {
device_printf(sc->dev, "Cannot stop clock\n");
goto clk_fail;
}
rv = tegra_powergate_power_on(id);
if (rv != 0) {
device_printf(sc->dev, "Cannot power on powergate\n");
goto clk_fail;
}
rv = clk_enable(clk);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable clock\n");
goto clk_fail;
}
DELAY(20);
rv = tegra_powergate_remove_clamping(id);
if (rv != 0) {
device_printf(sc->dev, "Cannot remove clamping\n");
goto fail;
}
rv = hwreset_deassert(rst);
if (rv != 0) {
device_printf(sc->dev, "Cannot unreset reset\n");
goto fail;
}
return 0;
fail:
clk_disable(clk);
clk_fail:
hwreset_assert(rst);
tegra_powergate_power_off(id);
return (rv);
}
int __init paz00_power_init(void)
{
int err;
err = paz00_regulator_init();
if (err < 0) {
pr_warning("Unable to initialize regulator\n");
return -1;
}
tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
return 0;
}
static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
{
struct tegra_ahci_priv *tegra = hpriv->plat_data;
ahci_platform_disable_resources(hpriv);
reset_control_assert(tegra->sata_rst);
reset_control_assert(tegra->sata_oob_rst);
reset_control_assert(tegra->sata_cold_rst);
clk_disable_unprepare(tegra->sata_clk);
tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
}
static void powerdown_handler(struct work_struct *work)
{
struct nvhost_module *mod;
mod = container_of(to_delayed_work(work), struct nvhost_module, powerdown);
mutex_lock(&mod->lock);
if ((atomic_read(&mod->refcount) == 0) && mod->powered) {
int i;
if (mod->func)
mod->func(mod, NVHOST_POWER_ACTION_OFF);
for (i = 0; i < mod->num_clks; i++) {
clk_disable(mod->clk[i]);
}
if (mod->powergate_id != -1) {
tegra_periph_reset_assert(mod->clk[0]);
tegra_powergate_power_off(mod->powergate_id);
}
mod->powered = false;
if (mod->parent)
nvhost_module_idle(mod->parent);
}
mutex_unlock(&mod->lock);
}
static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
{
struct tegra_ahci_priv *tegra = hpriv->plat_data;
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
tegra->supplies);
if (ret)
return ret;
ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
tegra->sata_clk,
tegra->sata_rst);
if (ret)
goto disable_regulators;
reset_control_assert(tegra->sata_oob_rst);
reset_control_assert(tegra->sata_cold_rst);
ret = ahci_platform_enable_resources(hpriv);
if (ret)
goto disable_power;
reset_control_deassert(tegra->sata_cold_rst);
reset_control_deassert(tegra->sata_oob_rst);
return 0;
disable_power:
clk_disable_unprepare(tegra->sata_clk);
tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
disable_regulators:
regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
return ret;
}
static void __init tegra_init_power(void)
{
tegra_powergate_power_off(TEGRA_POWERGATE_MPE);
tegra_powergate_power_off(TEGRA_POWERGATE_3D);
}
static int
enable_fdt_resources(struct tegra_ahci_sc *sc)
{
int rv;
rv = regulator_enable(sc->supply_hvdd);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'hvdd' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_vddio);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'vddio' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'avdd' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_target_5v);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'target-5v' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_target_12v);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'sc->target-12v' regulator\n");
return (rv);
}
/* Stop clocks */
clk_stop(sc->clk_sata);
clk_stop(sc->clk_sata_oob);
tegra_powergate_power_off(TEGRA_POWERGATE_SAX);
rv = hwreset_assert(sc->hwreset_sata);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata oob' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_sata_cold);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata cold' reset\n");
return (rv);
}
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX,
sc->clk_sata, sc->hwreset_sata);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'SAX' powergate\n");
return (rv);
}
rv = clk_enable(sc->clk_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'sata oob' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_cml);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'cml' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_pll_e);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'pll e' clock\n");
return (rv);
}
rv = hwreset_deassert(sc->hwreset_sata_cold);
if (rv != 0) {
device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n");
return (rv);
}
rv = hwreset_deassert(sc->hwreset_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n");
return (rv);
}
rv = phy_enable(sc->dev, sc->phy);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable SATA phy\n");
return (rv);
}
return (0);
}
static int
enable_fdt_resources(struct tegra_xhci_softc *sc)
{
int rv;
rv = hwreset_assert(sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n");
return (rv);
}
rv = regulator_enable(sc->supply_avddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avddio_pex' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_dvddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'dvddio_pex' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_usb);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_usb' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_pll_utmip);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_pll_utmip-5v' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_pll_erefe);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_pll_erefe' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_usb_ss_pll);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_usb_ss_pll' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_hvdd_usb_ss);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'hvdd_usb_ss' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_hvdd_usb_ss_pll_e);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'hvdd_usb_ss_pll_e' regulator\n");
return (rv);
}
/* Power off XUSB host and XUSB SS domains. */
rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n");
return (rv);
}
rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n");
return (rv);
}
/* Setup XUSB ss_src clock first */
clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0);
if (rv != 0)
return (rv);
/* The XUSB gate clock must be enabled before XUSBA can be powered. */
rv = clk_enable(sc->clk_xusb_gate);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_gate' clock\n");
return (rv);
}
/* Power on XUSB host and XUSB SS domains. */
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
sc->clk_xusb_host, sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n");
return (rv);
}
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
sc->clk_xusb_ss, sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerup 'xusba' domain\n");
return (rv);
}
/* Enable rest of clocks */
rv = clk_enable(sc->clk_xusb_falcon_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_falcon_src' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_xusb_fs_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_fs_src' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_xusb_hs_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_hs_src' clock\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_0 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_1);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_1 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_2);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_2 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb3_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB3_0 phy\n");
return (rv);
}
return (0);
}
