static int __devinit tile_edac_mc_probe(struct platform_device *pdev) { char hv_file[32]; int hv_devhdl; struct mem_ctl_info *mci; struct tile_edac_priv *priv; int rc; sprintf(hv_file, "mshim/%d", pdev->id); hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0); if (hv_devhdl < 0) { return -EINVAL; } /* A TILE MC has a single channel and one chip-select row. */ mci = edac_mc_alloc(sizeof(struct tile_edac_priv), TILE_EDAC_NR_CSROWS, TILE_EDAC_NR_CHANS, pdev->id); if (mci == NULL) return -ENOMEM; priv = mci->pvt_info; priv->node = pdev->id; priv->hv_devhdl = hv_devhdl; mci->dev = &pdev->dev; mci->mtype_cap = MEM_FLAG_DDR2; mci->edac_ctl_cap = EDAC_FLAG_SECDED; mci->mod_name = DRV_NAME; mci->ctl_name = "TILEPro_Memory_Controller"; mci->dev_name = dev_name(&pdev->dev); mci->edac_check = tile_edac_check; /* * Initialize the MC control structure 'csrows' table * with the mapping and control information. */ if (tile_edac_init_csrows(mci)) { /* No csrows found. */ mci->edac_cap = EDAC_FLAG_NONE; } else { mci->edac_cap = EDAC_FLAG_SECDED; } platform_set_drvdata(pdev, mci); /* Register with EDAC core */ rc = edac_mc_add_mc(mci); if (rc) { dev_err(&pdev->dev, "failed to register with EDAC core\n"); edac_mc_free(mci); return rc; } return 0; }
static int __devinit tile_edac_mc_probe(struct platform_device *pdev) { char hv_file[32]; int hv_devhdl; struct mem_ctl_info *mci; struct tile_edac_priv *priv; int rc; sprintf(hv_file, "mshim/%d", pdev->id); hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0); if (hv_devhdl < 0) return -EINVAL; mci = edac_mc_alloc(sizeof(struct tile_edac_priv), TILE_EDAC_NR_CSROWS, TILE_EDAC_NR_CHANS, pdev->id); if (mci == NULL) return -ENOMEM; priv = mci->pvt_info; priv->node = pdev->id; priv->hv_devhdl = hv_devhdl; mci->dev = &pdev->dev; mci->mtype_cap = MEM_FLAG_DDR2; mci->edac_ctl_cap = EDAC_FLAG_SECDED; mci->mod_name = DRV_NAME; #ifdef __tilegx__ mci->ctl_name = "TILEGx_Memory_Controller"; #else mci->ctl_name = "TILEPro_Memory_Controller"; #endif mci->dev_name = dev_name(&pdev->dev); mci->edac_check = tile_edac_check; if (tile_edac_init_csrows(mci)) { mci->edac_cap = EDAC_FLAG_NONE; } else { mci->edac_cap = EDAC_FLAG_SECDED; } platform_set_drvdata(pdev, mci); rc = edac_mc_add_mc(mci); if (rc) { dev_err(&pdev->dev, "failed to register with EDAC core\n"); edac_mc_free(mci); return rc; } return 0; }
static int tile_edac_mc_probe(struct platform_device *pdev) { char hv_file[32]; int hv_devhdl; struct mem_ctl_info *mci; struct edac_mc_layer layers[2]; struct tile_edac_priv *priv; int rc; sprintf(hv_file, "mshim/%d", pdev->id); hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0); if (hv_devhdl < 0) return -EINVAL; /* A TILE MC has a single channel and one chip-select row. */ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers[0].size = TILE_EDAC_NR_CSROWS; layers[0].is_virt_csrow = true; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = TILE_EDAC_NR_CHANS; layers[1].is_virt_csrow = false; mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, sizeof(struct tile_edac_priv)); if (mci == NULL) return -ENOMEM; priv = mci->pvt_info; priv->node = pdev->id; priv->hv_devhdl = hv_devhdl; mci->pdev = &pdev->dev; mci->mtype_cap = MEM_FLAG_DDR2; mci->edac_ctl_cap = EDAC_FLAG_SECDED; mci->mod_name = DRV_NAME; #ifdef __tilegx__ mci->ctl_name = "TILEGx_Memory_Controller"; #else mci->ctl_name = "TILEPro_Memory_Controller"; #endif mci->dev_name = dev_name(&pdev->dev); mci->edac_check = tile_edac_check; /* * Initialize the MC control structure 'csrows' table * with the mapping and control information. */ if (tile_edac_init_csrows(mci)) { /* No csrows found. */ mci->edac_cap = EDAC_FLAG_NONE; } else { mci->edac_cap = EDAC_FLAG_SECDED; } platform_set_drvdata(pdev, mci); /* Register with EDAC core */ rc = edac_mc_add_mc(mci); if (rc) { dev_err(&pdev->dev, "failed to register with EDAC core\n"); edac_mc_free(mci); return rc; } return 0; }