void timer_setup(void)
{
/* Enable timer clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
/* Reset timer. */
timer_reset(TIM1);
/* Configure prescaler. */
timer_set_prescaler(TIM1, 160);
/* Configure PE11 (AF1: TIM1_CH2) (SYNC_IN). */
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
gpio_mode_setup(GPIOE, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11);
gpio_set_af(GPIOE, GPIO_AF1, GPIO11);
/* Configure input capture. */
timer_ic_disable(TIM1, TIM_IC2);
timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2);
timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING);
timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF);
timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF);
timer_ic_enable(TIM1, TIM_IC2);
/* Enable counter. */
timer_enable_counter(TIM1);
/* Enable IRQs */
nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ);
timer_enable_irq(TIM1, TIM_DIER_UIE);
nvic_enable_irq(NVIC_TIM1_CC_IRQ);
timer_enable_irq(TIM1, TIM_DIER_CC2IE);
}
void torture_setup ( void ) {
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
timer_reset(TIM3);
// 24Mhz / 10khz -1.
timer_set_prescaler(TIM3, 20000); // 24Mhz/10000hz - 1
// 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts
timer_set_period(TIM3, 1);
/* Set timer start value. */
TIM_CNT(TIM3) = 1;
/* Set timer prescaler. */
TIM_PSC(TIM3) = 100; // 100 .. so about 840000 ticks per second
/* End timer value. If this is reached an interrupt is generated. */
TIM_ARR(TIM3) = 60; // 840000/14 -> 60,000/sec
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_enable_update_event(TIM3); // default at reset!
timer_enable_irq(TIM3, TIM_DIER_UIE);
timer_enable_counter(TIM3);
}
/**
* @brief Attach a timer interrupt.
* @param dev Timer device
* @param interrupt Interrupt number to attach to; this may be any
* timer_interrupt_id or timer_channel value appropriate
* for the timer.
* @param handler Handler to attach to the given interrupt.
* @see timer_interrupt_id
* @see timer_channel
*/
void timer_attach_interrupt(timer_dev *dev,
uint8 interrupt,
voidFuncPtr handler) {
dev->handlers[interrupt] = handler;
timer_enable_irq(dev, interrupt);
enable_irq(dev, interrupt);
}
/*
* Read a character from the UART RX and stuff it in a software FIFO.
* Allowed to read from FIFO out pointer, but not write to it.
* Allowed to write to FIFO in pointer.
*/
void USBUSART_ISR(void)
{
char c = usart_recv(USBUSART);
/* Turn on LED */
gpio_set(LED_PORT_UART, LED_UART);
/* If the next increment of rx_in would put it at the same point
* as rx_out, the FIFO is considered full.
*/
if (((buf_rx_in + 1) % FIFO_SIZE) != buf_rx_out)
{
/* insert into FIFO */
buf_rx[buf_rx_in++] = c;
/* wrap out pointer */
if (buf_rx_in >= FIFO_SIZE)
{
buf_rx_in = 0;
}
/* enable deferred processing if we put data in the FIFO */
timer_enable_irq(USBUSART_TIM, TIM_DIER_UIE);
}
}
static void pwm_setup(void) {
/* Configure GPIOs: OUT=PA7 */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM3_CH2 );
timer_reset(TIM3);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_disable_oc_output(TIM3, TIM_OC2);
timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
timer_disable_oc_clear(TIM3, TIM_OC2);
timer_set_oc_value(TIM3, TIM_OC2, 0);
timer_enable_oc_preload(TIM3, TIM_OC2);
timer_set_oc_polarity_high(TIM3, TIM_OC2);
timer_enable_oc_output(TIM3, TIM_OC2);
timer_set_dma_on_update_event(TIM3);
timer_enable_irq(TIM3, TIM_DIER_UDE); // in fact, enable DMA on update
timer_enable_preload(TIM3);
timer_continuous_mode(TIM3);
timer_set_period(TIM3, WSP);
timer_enable_counter(TIM3);
}
int main(void)
{
rcc_clock_setup_in_hse_8mhz_out_72mhz();
gpio_setup();
timer_setup();
/*
* The goal is to let the LED2 glow for a second and then be
* off for a second.
*/
while (1) /* Halt. */
{
/* Update interrupt enable. */
timer_enable_irq(TIM2, TIM_DIER_UIE);
/* Start timer. */
timer_enable_counter(TIM2);
// gpio_toggle(GPIOB, GPIO9); /* LED on/off */
/* Delay for 1 second LED flashes */
// int i;
// for (i = 0; i < 6400000; i++) /* Wait a bit. */
// __asm__("nop");
}
return 0;
}
/******************************************************************************
Initializes the timer, turn on the interrupt and put the interrupt time to zero
INPUT void
OUTPUT void
The timer is set to roll over at 0.5 second from an 8us clock, and the output
compare 1 is used to trigger an alarm. This is set progressively by the
CanFestival stack.
******************************************************************************/
void initTimer(void)
{
/* Set alarm back to zero */
timerAlarm = 0;
/* Enable TIM3 clock. */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
/* Enable TIM3 interrupt. */
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_reset(TIM3);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Set prescaler to give 8us clock */
timer_set_prescaler(TIM3, 576);
/* Set the period as 0.5 second */
timer_set_period(TIM3, TIMEVAL_MAX);
/* Disable physical pin outputs. */
timer_disable_oc_output(TIM3, TIM_OC1 | TIM_OC2 | TIM_OC3 | TIM_OC4);
/* Configure global mode of output channel 1, disabling the output. */
timer_disable_oc_clear(TIM3, TIM_OC1);
timer_disable_oc_preload(TIM3, TIM_OC1);
timer_set_oc_slow_mode(TIM3, TIM_OC1);
timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_FROZEN);
/* Set the initial compare value for OC1. */
timer_set_oc_value(TIM3, TIM_OC1, timerAlarm);
/* Continous counting mode. */
timer_continuous_mode(TIM3);
/* ARR reload disable. */
timer_disable_preload(TIM3);
/* Counter enable. */
timer_enable_counter(TIM3);
/* Enable compare match interrupt. */
timer_enable_irq(TIM3, TIM_DIER_CC1IE);
}
static void pwm_timer_init(pwm_callback update_callback) {
/** timer config **/
rcc_periph_clock_enable(RCC_TIM2);
timer_reset(TIM2);
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_prescaler(TIM2, 0);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_PWM1);
timer_set_oc_mode(TIM2, TIM_OC2, TIM_OCM_PWM2);
timer_enable_oc_output(TIM2, TIM_OC1);
timer_enable_oc_output(TIM2, TIM_OC2);
timer_set_period(TIM2, 1024-1);
timer_set_oc_value(TIM2, TIM_OC1, 0);
timer_set_oc_value(TIM2, TIM_OC2, 0);
timer_enable_counter(TIM2);
if ( update_callback != 0 ) {
pwm_update_callback = update_callback;
nvic_enable_irq(NVIC_TIM2_IRQ);
timer_enable_irq(TIM2, TIM_DIER_UIE);
}
}
/**
* Setup stepper motors' timer Tim
* N == 0 for TIM3, == 1 for TIM4
*/
static void setup_timer(uint8_t N){
uint32_t Tim;
switch (N){
case 0:
Tim = TIM3;
nvic_enable_irq(NVIC_TIM3_IRQ);
break;
case 1:
Tim = TIM4;
nvic_enable_irq(NVIC_TIM4_IRQ);
break;
default:
return;
}
timer_reset(Tim);
// timers have frequency of 2MHz, 2 pulse == 1 microstep
// 36MHz of APB1
timer_set_mode(Tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
// 72MHz div 36 = 2MHz
timer_set_prescaler(Tim, 35); // prescaler is (div - 1), 2pulse == 1 step
timer_continuous_mode(Tim); // automatically reload
timer_disable_preload(Tim); // force changing period
timer_set_period(Tim, Motor_period[N] - 1);
timer_enable_update_event(Tim);
timer_enable_irq(Tim, TIM_DIER_UIE); // update IRQ enable
timer_enable_counter(Tim);
timers_activated[N] = 1;
#ifdef EBUG
if(mode == BYTE_MODE){
lastsendfun('3' + N);
P(" timer\n", lastsendfun);
}
#endif
}
void funcgen_plat_timer_setup(int channel, int period_ns) {
uint32_t timer;
switch (channel) {
case 1: timer = TIM7;
break;
case 0:
default:
timer = TIM6;
break;
}
timer_reset(timer);
// APB is maxed at 42Mhz, so APB timers run at 84Mhz
// dac says 1msps max max, so at 1msps, we want a period of what, 1 Mhz _overflows_
// so at least 2 Mhz clock..., let's say 4 Mhz timer clock for max res stuff
// want to run the clock pretty quick, let's say 50ns steps or so at the bottom end,
// at ~24Mhz or similar,
// this is _F4_ specific!
/* two ranges is probably su*/
if (period_ns > 50) {
timer_set_prescaler(timer, 3); // 84 / 21 - 1 ticks at ~48ns
timer_set_period(timer, (period_ns / 48) - 1);
}
// if (period_ns * 50 > 0x6000) {
// /* don't even try and run that fast with this slow a wave */
// timer_set_prescaler(timer, 83); // 1Mhz (84/1 - 1) ticks at 1usecs
// timer_set_period(timer, (period_ns / 1000) - 1);
// }
timer_enable_irq(timer, TIM_DIER_UIE);
timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE);
timer_enable_counter(timer);
}
static void tim_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value. */
timer_set_prescaler(TIM2, 36000);
/* Enable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ---- */
/* ARR reload enable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
}
static void platform_init_eventtimer() {
/* Set up TIM2 as 32bit clock */
timer_reset(TIM2);
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(TIM2, 0xFFFFFFFF);
timer_set_prescaler(TIM2, 0);
timer_disable_preload(TIM2);
timer_continuous_mode(TIM2);
/* Setup output compare registers */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Setup input captures for CH2-4 Triggers */
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO3);
gpio_set_af(GPIOB, GPIO_AF1, GPIO3);
timer_ic_set_input(TIM2, TIM_IC2, TIM_IC_IN_TI2);
timer_ic_set_filter(TIM2, TIM_IC2, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC2, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC2);
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO10);
gpio_set_af(GPIOB, GPIO_AF1, GPIO10);
timer_ic_set_input(TIM2, TIM_IC3, TIM_IC_IN_TI3);
timer_ic_set_filter(TIM2, TIM_IC3, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC3, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC3);
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11);
gpio_set_af(GPIOB, GPIO_AF1, GPIO11);
timer_ic_set_input(TIM2, TIM_IC4, TIM_IC_IN_TI4);
timer_ic_set_filter(TIM2, TIM_IC4, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC4, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC4);
timer_enable_counter(TIM2);
timer_enable_irq(TIM2, TIM_DIER_CC2IE);
timer_enable_irq(TIM2, TIM_DIER_CC3IE);
timer_enable_irq(TIM2, TIM_DIER_CC4IE);
nvic_enable_irq(NVIC_TIM2_IRQ);
nvic_set_priority(NVIC_TIM2_IRQ, 0);
}
/* ----------------------- Enable Timer -----------------------------*/
inline void
vMBPortTimersEnable( )
{
/* Restart the timer with the period value set in xMBPortTimersInit( ) */
TIM2_CNT = 0;
timer_enable_irq(TIM2, TIM_DIER_UIE);
timer_enable_counter(TIM2);
}
/* Function to init a timer */
void timer_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value.
* Running the clock at 5kHz.
*/
/*
* On STM32F4 the timers are not running directly from pure APB1 or
* APB2 clock busses. The APB1 and APB2 clocks used for timers might
* be the double of the APB1 and APB2 clocks. This depends on the
* setting in DCKCFGR register. By default the behaviour is the
* following: If the Prescaler APBx is greater than 1 the derived timer
* APBx clocks will be double of the original APBx frequencies. Only if
* the APBx prescaler is set to 1 the derived timer APBx will equal the
* original APBx frequencies.
*
* In our case here the APB1 is devided by 4 system frequency and APB2
* divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will
* be 2 x APB2. So when we try to calculate the prescaler value we have
* to use rcc_apb1_freqency * 2!!!
*
* For additional information see reference manual for the stm32f4
* familiy of chips. Page 204 and 213
*/
timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000));
/* Disable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 100);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable update interrupt. */
timer_enable_irq(TIM2, TIM_DIER_UIE);
}
void ppm_arch_init ( void ) {
/* timer clock enable */
rcc_peripheral_enable_clock(PPM_RCC, PPM_PERIPHERAL);
/* GPIOA clock enable */
rcc_peripheral_enable_clock(&RCC_APB2ENR, PPM_GPIO_PERIPHERAL);
/* timer gpio configuration */
gpio_set_mode(PPM_GPIO_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, PPM_GPIO_PIN);
/* Time Base configuration */
timer_reset(PPM_TIMER);
timer_set_mode(PPM_TIMER, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(PPM_TIMER, 0xFFFF);
/* run ppm timer at cpu freq / 9 = 8MHz */
timer_set_prescaler(PPM_TIMER, 8);
/* TIM configuration: Input Capture mode ---------------------
The Rising edge is used as active edge,
Intput pin is either PA1 or PA10
------------------------------------------------------------ */
#if defined PPM_PULSE_TYPE && PPM_PULSE_TYPE == PPM_PULSE_TYPE_POSITIVE
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_RISING);
#elif defined PPM_PULSE_TYPE && PPM_PULSE_TYPE == PPM_PULSE_TYPE_NEGATIVE
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_FALLING);
#else
#error "Unknown PM_PULSE_TYPE"
#endif
timer_ic_set_input(PPM_TIMER, PPM_CHANNEL, PPM_TIMER_INPUT);
timer_ic_set_prescaler(PPM_TIMER, PPM_CHANNEL, TIM_IC_PSC_OFF);
timer_ic_set_filter(PPM_TIMER, PPM_CHANNEL, TIM_IC_OFF);
/* Enable timer Interrupt(s). */
nvic_set_priority(PPM_IRQ, 2);
nvic_enable_irq(PPM_IRQ);
#ifdef PPM_IRQ2
nvic_set_priority(PPM_IRQ2, 2);
nvic_enable_irq(PPM_IRQ2);
#endif
/* Enable the CC2 and Update interrupt requests. */
timer_enable_irq(PPM_TIMER, PPM_IRQ_FLAGS);
/* Enable capture channel. */
timer_ic_enable(PPM_TIMER, PPM_CHANNEL);
/* TIM enable counter */
timer_enable_counter(PPM_TIMER);
ppm_last_pulse_time = 0;
ppm_cur_pulse = RADIO_CONTROL_NB_CHANNEL;
timer_rollover_cnt = 0;
}
void timer_setup() {
RCC_APB1ENR |= RCC_APB1ENR_TIM2EN;
timer_set_prescaler(TIM2, 1);
timer_set_period(TIM2, rcc_ppre1_frequency / 100);
timer_enable_irq(TIM2, TIM_DIER_UIE);
TIM2_CNT = 0;
timer_enable_counter(TIM2);
nvic_enable_irq(NVIC_TIM2_IRQ);
}
void ppm_arch_init ( void ) {
/* timer clock enable */
rcc_peripheral_enable_clock(PPM_RCC, PPM_PERIPHERAL);
/* GPIO clock enable */
gpio_enable_clock(PPM_GPIO_PORT);
/* timer gpio configuration */
gpio_setup_pin_af(PPM_GPIO_PORT, PPM_GPIO_PIN, PPM_GPIO_AF, FALSE);
/* Time Base configuration */
timer_reset(PPM_TIMER);
timer_set_mode(PPM_TIMER, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(PPM_TIMER, 0xFFFF);
timer_set_prescaler(PPM_TIMER, (PPM_TIMER_CLK / (RC_PPM_TICKS_PER_USEC*ONE_MHZ_CLK)) - 1);
/* TIM configuration: Input Capture mode ---------------------
The Rising edge is used as active edge
------------------------------------------------------------ */
#if defined PPM_PULSE_TYPE && PPM_PULSE_TYPE == PPM_PULSE_TYPE_POSITIVE
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_RISING);
#elif defined PPM_PULSE_TYPE && PPM_PULSE_TYPE == PPM_PULSE_TYPE_NEGATIVE
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_FALLING);
#else
#error "Unknown PPM_PULSE_TYPE"
#endif
timer_ic_set_input(PPM_TIMER, PPM_CHANNEL, PPM_TIMER_INPUT);
timer_ic_set_prescaler(PPM_TIMER, PPM_CHANNEL, TIM_IC_PSC_OFF);
timer_ic_set_filter(PPM_TIMER, PPM_CHANNEL, TIM_IC_OFF);
/* Enable timer Interrupt(s). */
nvic_set_priority(PPM_IRQ, 2);
nvic_enable_irq(PPM_IRQ);
#ifdef PPM_IRQ2
nvic_set_priority(PPM_IRQ2, 2);
nvic_enable_irq(PPM_IRQ2);
#endif
/* Enable the Capture/Compare and Update interrupt requests. */
timer_enable_irq(PPM_TIMER, (PPM_CC_IE | TIM_DIER_UIE));
/* Enable capture channel. */
timer_ic_enable(PPM_TIMER, PPM_CHANNEL);
/* TIM enable counter */
timer_enable_counter(PPM_TIMER);
ppm_last_pulse_time = 0;
ppm_cur_pulse = RADIO_CONTROL_NB_CHANNEL;
timer_rollover_cnt = 0;
}
/**
* We set this timer to count uSecs.
* The interrupt is only to indicate that it timed out and to shut itself off.
*/
void setup_tim7(void)
{
timer_clear_flag(TIM7, TIM_SR_UIF);
TIM7_CNT = 1;
timer_set_prescaler(TIM7, 23); // 24Mhz/1Mhz - 1
timer_set_period(TIM7, RHT_INTER_BIT_TIMEOUT_USEC);
timer_enable_irq(TIM7, TIM_DIER_UIE);
nvic_enable_irq(NVIC_TIM7_IRQ);
timer_enable_counter(TIM7);
}
/** PWM arch init called by generic pwm driver
*/
void actuators_dualpwm_arch_init(void)
{
/*-----------------------------------
* Configure timer peripheral clocks
*-----------------------------------*/
#if PWM_USE_TIM1
rcc_periph_clock_enable(RCC_TIM1);
#endif
#if PWM_USE_TIM2
rcc_periph_clock_enable(RCC_TIM2);
#endif
#if PWM_USE_TIM3
rcc_periph_clock_enable(RCC_TIM3);
#endif
#if PWM_USE_TIM4
rcc_periph_clock_enable(RCC_TIM4);
#endif
#if PWM_USE_TIM5
rcc_periph_clock_enable(RCC_TIM5);
#endif
#if PWM_USE_TIM8
rcc_periph_clock_enable(RCC_TIM8);
#endif
#if PWM_USE_TIM9
rcc_periph_clock_enable(RCC_TIM9);
#endif
#if PWM_USE_TIM12
rcc_periph_clock_enable(RCC_TIM12);
#endif
/*----------------
* Configure GPIO
*----------------*/
#ifdef DUAL_PWM_SERVO_5
gpio_setup_pin_af(DUAL_PWM_SERVO_5_GPIO, DUAL_PWM_SERVO_5_PIN, DUAL_PWM_SERVO_5_AF, TRUE);
#endif
#ifdef DUAL_PWM_SERVO_6
gpio_setup_pin_af(DUAL_PWM_SERVO_6_GPIO, DUAL_PWM_SERVO_6_PIN, DUAL_PWM_SERVO_6_AF, TRUE);
#endif
#if DUAL_PWM_USE_TIM5
set_servo_timer(TIM5, TIM5_SERVO_HZ, PWM_TIM5_CHAN_MASK);
nvic_set_priority(NVIC_TIM5_IRQ, 2);
nvic_enable_irq(NVIC_TIM5_IRQ);
timer_enable_irq(TIM5, TIM_DIER_CC1IE);
#endif
//calculation the values to put into the timer registers to generate pulses every 4ms and 16ms.
ratio_4ms = (ONE_MHZ_CLK / 250) - 1;
ratio_16ms = (ONE_MHZ_CLK / 62.5) - 1;
}
void freq_capture_setup(void) {
/* Configure PE11 (AF1: TIM1_CH2) (SYNC_IN). */
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
gpio_mode_setup(GPIOE, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11);
gpio_set_af(GPIOE, GPIO_AF1, GPIO11);
/* Timer1: Input compare */
/* Enable timer clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
/* Reset timer. */
timer_reset(TIM1);
/* Configure timer1. */
timer_set_mode(TIM1,
TIM_CR1_CKD_CK_INT, // Internal clock
TIM_CR1_CMS_EDGE, // Edge synchronization
TIM_CR1_DIR_UP); // Count upward
timer_set_prescaler(TIM1, TIMER1_PRESCALER);
timer_set_period(TIM1, TIMER1_PERIOD); //Sets TIM1_ARR
timer_continuous_mode(TIM1);
/* Configure PE13: Toggle pin on falling edge via interrupt */
//rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
//gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, GPIO13);
/* Configure input capture. */
timer_ic_disable(TIM1, TIM_IC2);
timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING);
timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF);
timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2);
// See RM, p. 561: digital filter
//timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_DTF_DIV_32_N_8);
timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF);
timer_ic_enable(TIM1, TIM_IC2);
/* Enable counter. */
timer_enable_counter(TIM1);
timer_clear_flag (TIM1, TIM_SR_CC2IF);
/* Enable IRQs */
nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ);
timer_enable_irq(TIM1, TIM_DIER_UIE);
nvic_enable_irq(NVIC_TIM1_CC_IRQ);
timer_enable_irq(TIM1, TIM_DIER_CC2IE);
}
/*
* Another ms timer, this one used to generate an overflow interrupt at 1ms
* It is used to toggle leds and write tick counts
*/
static void setup_tim6(void)
{
timer_reset(TIM6);
/* 24Mhz / 10khz -1. */
timer_set_prescaler(TIM6, 2399); /* 24Mhz/10000hz - 1 */
/* 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts */
timer_set_period(TIM6, 10);
nvic_enable_irq(NVIC_TIM6_IRQ);
timer_enable_update_event(TIM6); /* default at reset! */
timer_enable_irq(TIM6, TIM_DIER_UIE);
timer_enable_counter(TIM6);
}
void ppm_arch_init ( void ) {
/* timer clock enable */
rcc_peripheral_enable_clock(PPM_RCC, PPM_PERIPHERAL);
/* GPIOA clock enable */
rcc_peripheral_enable_clock(&RCC_APB2ENR, PPM_GPIO_PERIPHERAL);
/* timer gpio configuration */
gpio_set_mode(PPM_GPIO_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, PPM_GPIO_PIN);
/* Time Base configuration */
timer_reset(PPM_TIMER);
timer_set_mode(PPM_TIMER, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(PPM_TIMER, 0xFFFF);
timer_set_prescaler(PPM_TIMER, 0x8);
/* TIM2 configuration: Input Capture mode ---------------------
The external signal is connected to TIM2 CH2 pin (PA.01)
The Rising edge is used as active edge,
------------------------------------------------------------ */
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_RISING);
timer_ic_set_input(PPM_TIMER, PPM_CHANNEL, PPM_TIMER_INPUT);
timer_ic_set_prescaler(PPM_TIMER, PPM_CHANNEL, TIM_IC_PSC_OFF);
timer_ic_set_filter(PPM_TIMER, PPM_CHANNEL, TIM_IC_OFF);
/* Enable timer Interrupt(s). */
nvic_set_priority(PPM_IRQ, 2);
nvic_enable_irq(PPM_IRQ);
#ifdef PPM_IRQ2
nvic_set_priority(PPM_IRQ2, 2);
nvic_enable_irq(PPM_IRQ2);
#endif
/* Enable the CC2 and Update interrupt requests. */
timer_enable_irq(PPM_TIMER, PPM_IRQ_FLAGS);
/* Enable capture channel. */
timer_ic_enable(PPM_TIMER, PPM_CHANNEL);
/* TIM2 enable counter */
timer_enable_counter(PPM_TIMER);
ppm_last_pulse_time = 0;
ppm_cur_pulse = RADIO_CONTROL_NB_CHANNEL;
timer_rollover_cnt = 0;
}
/**
* Set the DSM timer to interrupt
* @param[in] us The time in microseconds divided by 10
*/
void timer_dsm_set(u16 us) {
#if DEBUG && !DSM_RECEIVER && !DSM_MITM
u16 new_t = (us*2 + timer_get_counter(TIMER_DSM)) & 65535;
#else
u16 new_t = (us + timer_get_counter(TIMER_DSM)) & 65535;
#endif
// Update the timer compare value 1
timer_set_oc_value(TIMER_DSM, TIM_OC1, new_t);
// Clear the interrupt flag and enable the interrupt of compare 1
timer_clear_flag(TIMER_DSM, TIM_SR_CC1IF);
timer_enable_irq(TIMER_DSM, TIM_DIER_CC1IE);
}
/* DMA1 Channel7 Interrupt Handler gets executed once the complete framebuffer has been transmitted to the LEDs */
void DMA1_Channel7_IRQHandler(void)
{
// clear DMA7 transfer complete interrupt flag
dma_clear_isr_bits(DMA1, DMA_CH7);
// enable TIM2 Update interrupt to append 50us dead period
timer_enable_irq(TIMER2, TIMER_UPDATE_INTERRUPT);
// disable the DMA channels
dma_disable(DMA1, DMA_CH2);
dma_disable(DMA1, DMA_CH5);
dma_disable(DMA1, DMA_CH7);
// IMPORTANT: disable the DMA requests, too!
timer_dma_disable_req(TIMER2, 1);
timer_dma_disable_req(TIMER2, 2);
timer_dma_disable_req(TIMER2, 0); /* TIM_DMA_Update */
}
void ws2812_send( void )
{
/* init the DMA data transfer */
dma_clear_interrupt_flags( DMA1, DMA_CHANNEL2, DMA_TEIF | DMA_HTIF | DMA_TCIF | DMA_GIF);
dma_clear_interrupt_flags( DMA1, DMA_CHANNEL3, DMA_TEIF | DMA_HTIF | DMA_TCIF | DMA_GIF);
dma_clear_interrupt_flags( DMA1, DMA_CHANNEL4, DMA_TEIF | DMA_HTIF | DMA_TCIF | DMA_GIF);
dma_set_memory_address( DMA1, DMA_CHANNEL4, (uint32_t)actual_bitframe);
dma_set_number_of_data( DMA1, DMA_CHANNEL2, WS2812_BUFFERSIZE);
dma_set_number_of_data( DMA1, DMA_CHANNEL3, WS2812_BUFFERSIZE);
dma_set_number_of_data( DMA1, DMA_CHANNEL4, WS2812_BUFFERSIZE);
TIM3_SR = 0;
dma_enable_channel( DMA1, DMA_CHANNEL2);
dma_enable_channel( DMA1, DMA_CHANNEL3);
dma_enable_channel( DMA1, DMA_CHANNEL4);
//timer_enable_irq( TIM3, TIM_DIER_TDE);
timer_enable_irq( TIM3, TIM_DIER_CC1DE);
timer_enable_irq( TIM3, TIM_DIER_CC3DE);
timer_enable_irq( TIM3, TIM_DIER_UDE);
timer_set_counter(TIM3, 60);
timer_enable_counter(TIM3);
SCB_ICSR |= SCB_ICSR_PENDSVSET;
}
void plc_wait_tmr_init(void)
{
//Wait timer config, basic timers TIM6 and TIM7 may be used
rcc_periph_clock_enable( PLC_WAIT_TMR_PERIPH );
timer_reset ( PLC_WAIT_TMR );
timer_set_prescaler ( PLC_WAIT_TMR, ((2*rcc_apb1_frequency)/1000000ul - 1)); //1MHz
timer_disable_preload ( PLC_WAIT_TMR );
timer_continuous_mode ( PLC_WAIT_TMR );
timer_set_period ( PLC_WAIT_TMR, 1000 ); //1KHz
timer_enable_counter ( PLC_WAIT_TMR );
timer_enable_irq ( PLC_WAIT_TMR, TIM_DIER_UIE);
nvic_enable_irq( PLC_WAIT_TMR_VECTOR );
}
/** @brief DMA2,3 callback
*
* callback function for DMA transfer
*/
void dma1_channel2_3_isr( void )
{
/* after DMA transfer completed enable timer 3 overflow */
dma_clear_interrupt_flags(DMA1, DMA_CHANNEL2, DMA_TCIF);
timer_enable_irq(TIM3, TIM_DIER_UIE);
dma_disable_channel( DMA1, DMA_CHANNEL2);
dma_disable_channel( DMA1, DMA_CHANNEL3);
dma_disable_channel( DMA1, DMA_CHANNEL4);
timer_disable_irq( TIM3, TIM_DIER_CC1DE);
timer_disable_irq( TIM3, TIM_DIER_CC3DE);
timer_disable_irq( TIM3, TIM_DIER_UDE);
}
void LED_init(void)
{
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
set_led(false);
timer_reset(TIM2);
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_prescaler(TIM2, 256);
timer_enable_preload(TIM2);
timer_one_shot_mode(TIM2);
timer_set_period(TIM2, (uint16_t)((rcc_ppre1_frequency/256) / 20));
timer_enable_irq(TIM2, TIM_DIER_UIE);
timer_clear_flag(TIM2, TIM_SR_UIF);
nvic_enable_irq(NVIC_TIM2_IRQ);
nvic_set_priority(NVIC_TIM2_IRQ, 128);
}
void baro_init()
{
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14);
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15);
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
deselect_slave();
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL,
SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
spi_enable_ss_output(SPI2);
spi_enable(SPI2);
dma_set_peripheral_address(DMA1, DMA_CHANNEL3, SPI2_DR);
dma_set_read_from_memory(DMA1, DMA_CHANNEL3);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3);
dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_8BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT);
dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH);
dma_set_peripheral_address(DMA1, DMA_CHANNEL4, SPI2_DR);
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL4);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL4);
dma_set_peripheral_size(DMA1, DMA_CHANNEL4, DMA_CCR_PSIZE_8BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL4, DMA_CCR_MSIZE_8BIT);
dma_set_priority(DMA1, DMA_CHANNEL4, DMA_CCR_PL_VERY_HIGH);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL4);
timer_reset(TIM4);
timer_enable_irq(TIM4, TIM_DIER_UIE);
timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* 3200 / 16 = 200 Hz */
timer_set_prescaler(TIM4, 32);
timer_set_period(TIM4, 5625);
nvic_set_priority(NVIC_TIM4_IRQ, 16 * 2);
nvic_set_priority(NVIC_DMA1_CHANNEL4_IRQ, 16 * 2);
nvic_enable_irq(NVIC_TIM4_IRQ);
nvic_enable_irq(NVIC_DMA1_CHANNEL4_IRQ);
read_calibration_data();
}
void timer_setup(void)
{
rcc_periph_clock_enable(RCC_TIM2);
nvic_enable_irq(NVIC_TIM2_IRQ);
nvic_set_priority(NVIC_TIM2_IRQ, 1);
timer_reset(TIM2);
/* Timer global mode: - No Divider, Alignment edge, Direction up */
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_continuous_mode(TIM2);
/* Set timer prescaler. 72MHz/1440 => 50000 counts per second. */
timer_set_prescaler(TIM2, 1440);
/* End timer value. When this is reached an interrupt is generated. */
timer_set_period(TIM2, BLINK_INTERVAL);
/* Update interrupt enable. */
timer_enable_irq(TIM2, TIM_DIER_UIE);
/* Start timer. */
timer_enable_counter(TIM2);
}
