static int __init tegra20_init_rtc(struct device_node *np) { int ret; ret = timer_of_init(np, &suspend_rtc_to); if (ret) return ret; return clocksource_register_hz(&suspend_rtc_clocksource, 1000); }
static int __init csky_mptimer_init(struct device_node *np) { int ret, cpu, cpu_rollback; struct timer_of *to = NULL; /* * Csky_mptimer is designed for C-SKY SMP multi-processors and * every core has it's own private irq and regs for clkevt and * clksrc. * * The regs is accessed by cpu instruction: mfcr/mtcr instead of * mmio map style. So we needn't mmio-address in dts, but we still * need to give clk and irq number. * * We use private irq for the mptimer and irq number is the same * for every core. So we use request_percpu_irq() in timer_of_init. */ csky_mptimer_irq = irq_of_parse_and_map(np, 0); if (csky_mptimer_irq <= 0) return -EINVAL; ret = request_percpu_irq(csky_mptimer_irq, csky_timer_interrupt, "csky_mp_timer", &csky_to); if (ret) return -EINVAL; for_each_possible_cpu(cpu) { to = per_cpu_ptr(&csky_to, cpu); ret = timer_of_init(np, to); if (ret) goto rollback; } clocksource_register_hz(&csky_clocksource, timer_of_rate(to)); sched_clock_register(sched_clock_read, 32, timer_of_rate(to)); ret = cpuhp_setup_state(CPUHP_AP_CSKY_TIMER_STARTING, "clockevents/csky/timer:starting", csky_mptimer_starting_cpu, csky_mptimer_dying_cpu); if (ret) return -EINVAL; return 0; rollback: for_each_possible_cpu(cpu_rollback) { if (cpu_rollback == cpu) break; to = per_cpu_ptr(&csky_to, cpu_rollback); timer_of_cleanup(to); } return -EINVAL; }
static int __init sun4i_timer_init(struct device_node *node) { int ret; u32 val; ret = timer_of_init(node, &to); if (ret) return ret; writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1)); writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), timer_of_base(&to) + TIMER_CTL_REG(1)); /* * sched_clock_register does not have priorities, and on sun6i and * later there is a better sched_clock registered by arm_arch_timer.c */ if (of_machine_is_compatible("allwinner,sun4i-a10") || of_machine_is_compatible("allwinner,sun5i-a13") || of_machine_is_compatible("allwinner,sun5i-a10s") || of_machine_is_compatible("allwinner,suniv-f1c100s")) sched_clock_register(sun4i_timer_sched_read, 32, timer_of_rate(&to)); ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1), node->name, timer_of_rate(&to), 350, 32, clocksource_mmio_readl_down); if (ret) { pr_err("Failed to register clocksource\n"); return ret; } writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), timer_of_base(&to) + TIMER_CTL_REG(0)); /* Make sure timer is stopped before playing with interrupts */ sun4i_clkevt_time_stop(timer_of_base(&to), 0); /* clear timer0 interrupt */ sun4i_timer_clear_interrupt(timer_of_base(&to)); clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), TIMER_SYNC_TICKS, 0xffffffff); /* Enable timer0 interrupt */ val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG); writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG); return ret; }
static int __init tegra_init_timer(struct device_node *np, bool tegra20) { struct timer_of *to; int cpu, ret; to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); if (ret) goto out; timer_reg_base = timer_of_base(to); /* * Configure microsecond timers to have 1MHz clock * Config register is 0xqqww, where qq is "dividend", ww is "divisor" * Uses n+1 scheme */ switch (timer_of_rate(to)) { case 12000000: usec_config = 0x000b; /* (11+1)/(0+1) */ break; case 12800000: usec_config = 0x043f; /* (63+1)/(4+1) */ break; case 13000000: usec_config = 0x000c; /* (12+1)/(0+1) */ break; case 16800000: usec_config = 0x0453; /* (83+1)/(4+1) */ break; case 19200000: usec_config = 0x045f; /* (95+1)/(4+1) */ break; case 26000000: usec_config = 0x0019; /* (25+1)/(0+1) */ break; case 38400000: usec_config = 0x04bf; /* (191+1)/(4+1) */ break; case 48000000: usec_config = 0x002f; /* (47+1)/(0+1) */ break; default: ret = -EINVAL; goto out; } writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); unsigned int base = tegra_base_for_cpu(cpu, tegra20); unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); /* * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the * parent clock. */ if (tegra20) cpu_to->of_clk.rate = 1000000; cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + base; cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { pr_err("failed to map irq for cpu%d\n", cpu); ret = -EINVAL; goto out_irq; } irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, IRQF_TIMER | IRQF_NOBALANCING, cpu_to->clkevt.name, &cpu_to->clkevt); if (ret) { pr_err("failed to set up irq for cpu%d: %d\n", cpu, ret); irq_dispose_mapping(cpu_to->clkevt.irq); cpu_to->clkevt.irq = 0; goto out_irq; } } sched_clock_register(tegra_read_sched_clock, 32, 1000000); ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up); if (ret) pr_err("failed to register clocksource: %d\n", ret); #ifdef CONFIG_ARM register_current_timer_delay(&tegra_delay_timer); #endif ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, tegra_timer_stop); if (ret) pr_err("failed to set up cpu hp state: %d\n", ret); return ret; out_irq: for_each_possible_cpu(cpu) { struct timer_of *cpu_to; cpu_to = per_cpu_ptr(&tegra_to, cpu); if (cpu_to->clkevt.irq) { free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt); irq_dispose_mapping(cpu_to->clkevt.irq); } } out: timer_of_cleanup(to); return ret; }