void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
tlb_flush_page(env, env->pregs[PR_SPC]);
tlb_flush_page(env, new_spc);
#endif
}
/* Set Prefix */
void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
uint32_t prefix = a1 & 0x7fffe000;
env->psa = prefix;
qemu_log("prefix: %#x\n", prefix);
tlb_flush_page(env, 0);
tlb_flush_page(env, TARGET_PAGE_SIZE);
}
/* Set Prefix */
void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
uint32_t prefix;
prefix = cpu_ldl_data(env, a1);
env->psa = prefix & 0xfffff000;
qemu_log("prefix: %#x\n", prefix);
tlb_flush_page(env, 0);
tlb_flush_page(env, TARGET_PAGE_SIZE);
}
/* Set Prefix */
void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
CPUState *cs = CPU(s390_env_get_cpu(env));
uint32_t prefix = a1 & 0x7fffe000;
env->psa = prefix;
qemu_log("prefix: %#x\n", prefix);
tlb_flush_page(cs, 0);
tlb_flush_page(cs, TARGET_PAGE_SIZE);
}
void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
CRISCPU *cpu = cris_env_get_cpu(env);
CPUState *cs = CPU(cpu);
tlb_flush_page(cs, env->pregs[PR_SPC]);
tlb_flush_page(cs, new_spc);
#endif
}
void helper_invlpg(CPUX86State *env, target_ulong addr)
{
X86CPU *cpu = x86_env_get_cpu(env);
cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC());
tlb_flush_page(CPU(cpu), addr);
}
void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
#if !defined(CONFIG_USER_ONLY)
CRISCPU *cpu = cris_env_get_cpu(env);
#endif
uint32_t srs;
srs = env->pregs[PR_SRS];
srs &= 3;
env->sregs[srs][sreg] = env->regs[reg];
#if !defined(CONFIG_USER_ONLY)
if (srs == 1 || srs == 2) {
if (sreg == 6) {
/* Writes to tlb-hi write to mm_cause as a side
effect. */
env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
}
else if (sreg == 5) {
uint32_t set;
uint32_t idx;
uint32_t lo, hi;
uint32_t vaddr;
int tlb_v;
idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
set >>= 4;
set &= 3;
idx &= 15;
/* We've just made a write to tlb_lo. */
lo = env->sregs[SFR_RW_MM_TLB_LO];
/* Writes are done via r_mm_cause. */
hi = env->sregs[SFR_R_MM_CAUSE];
vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
13, 31);
vaddr <<= TARGET_PAGE_BITS;
tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
3, 3);
env->tlbsets[srs - 1][set][idx].lo = lo;
env->tlbsets[srs - 1][set][idx].hi = hi;
D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
vaddr, tlb_v, env->pc);
if (tlb_v) {
tlb_flush_page(CPU(cpu), vaddr);
}
}
}