static void tnetw1130_write0l(tnetw1130_t *s, hwaddr addr,
uint32_t value)
{
if (addr < TNETW1130_MEM0_SIZE) {
reg_write32(s->mem0, addr, value);
}
if (addr == TNETW1130_SLV_MEM_ADDR) {
s->fw_addr = value;
if (value >= TNETW1130_FW_SIZE) {
UNEXPECTED();
}
} else if (addr == TNETW1130_SLV_MEM_DATA) {
reg_write32(s->fw, s->fw_addr, value);
} else if (addr == TNETW1130_SLV_MEM_CTL) {
if (value == 0) {
TRACE(TNETW, logout("basic mode\n"));
} else if (value == 1) {
TRACE(TNETW, logout("autoincrement mode\n"));
MISSING();
} else {
UNEXPECTED();
}
} else if (addr == TNETW1130_SLV_END_CTL) {
}
TRACE(TNETW, logout("addr %s = 0x%08x\n", tnetw1130_regname(addr), value));
}
static void tnetw1130_write0b(tnetw1130_t *s, hwaddr addr,
uint8_t value)
{
if (addr < TNETW1130_MEM0_SIZE) {
s->mem0[addr] = value;
} else {
UNEXPECTED();
}
TRACE(TNETW, logout("addr %s = 0x%02x\n", tnetw1130_regname(addr), value));
}
static void tnetw1130_write0b(pci_tnetw1130_t * d, target_phys_addr_t addr,
uint8_t value)
{
tnetw1130_t *s = &d->tnetw1130;
if (addr < TNETW1130_MEM0_SIZE) {
s->mem0[addr] = value;
} else {
UNEXPECTED();
}
TRACE(TNETW, logout("addr %s = 0x%02x\n", tnetw1130_regname(addr), value));
}
static uint8_t tnetw1130_read0b(tnetw1130_t *s, hwaddr addr)
{
uint8_t value = 0;
if (addr < TNETW1130_MEM0_SIZE) {
value = s->mem0[addr];
} else {
UNEXPECTED();
}
//~ } else if (addr -= 0x20000, addr == TNETW1130_SOFT_RESET) {
TRACE(TNETW, logout("addr %s = 0x%02x\n", tnetw1130_regname(addr), value));
return value;
}
static uint8_t tnetw1130_read0b(pci_tnetw1130_t * d, target_phys_addr_t addr)
{
tnetw1130_t *s = &d->tnetw1130;
uint8_t value = 0;
if (addr < TNETW1130_MEM0_SIZE) {
value = s->mem0[addr];
} else {
UNEXPECTED();
}
//~ } else if (addr -= 0x20000, addr == TNETW1130_SOFT_RESET) {
TRACE(TNETW, logout("addr %s = 0x%02x\n", tnetw1130_regname(addr), value));
return value;
}
static uint32_t tnetw1130_read0l(tnetw1130_t *s, hwaddr addr)
{
uint32_t value = 0;
assert(addr < TNETW1130_MEM0_SIZE);
value = reg_read32(s->mem0, addr);
if (0) {
} else if (addr == TNETW1130_SLV_MEM_DATA) {
value = reg_read32(s->fw, s->fw_addr);
} else if (addr == TNETW1130_CMD_MAILBOX_OFFS) {
value = CMD_MAILBOX;
} else if (addr == TNETW1130_INFO_MAILBOX_OFFS) {
value = INFO_MAILBOX;
}
TRACE(TNETW, logout("addr %s = 0x%08x\n", tnetw1130_regname(addr), value));
return value;
}
static uint16_t tnetw1130_read0w(tnetw1130_t *s, hwaddr addr)
{
uint16_t value = 0;
if (addr < TNETW1130_MEM0_SIZE) {
value = reg_read16(s->mem0, addr);
}
if (0) {
} else if (addr == TNETW1130_SOFT_RESET) {
} else if (addr == TNETW1130_IRQ_STATUS_NON_DES) {
/* !!! set after eCPU start */
value = s->irq_status;
} else if (addr == TNETW1130_EE_START) {
} else if (addr == TNETW1130_ECPU_CTRL) {
} else if (addr == TNETW1130_EEPROM_CTL) {
value = 0;
} else if (addr == TNETW1130_EEPROM_INFORMATION) {
value = (RADIO_RADIA_16 << 8) + 0x01;
}
TRACE(TNETW, logout("addr %s = 0x%04x\n", tnetw1130_regname(addr), value));
return value;
}
static void tnetw1130_write0w(pci_tnetw1130_t * d, target_phys_addr_t addr,
uint16_t value)
{
tnetw1130_t *s = &d->tnetw1130;
if (addr < TNETW1130_MEM0_SIZE) {
reg_write16(s->mem0, addr, value);
} else {
UNEXPECTED();
}
if (addr == TNETW1130_SOFT_RESET) {
if (value & 1) {
TRACE(TNETW, logout("soft reset\n"));
}
} else if (addr == TNETW1130_INT_TRIG) {
if (value == 1) {
TRACE(TNETW, logout("trigger interrupt, status, cmd = %s\n",
tnetw1130_cmdname(reg_read16(s->mem1, CMD_MAILBOX))));
tnetw1130_cmd(s);
} else {
UNEXPECTED();
}
} else if (addr == TNETW1130_IRQ_ACK) {
/* !!! must reset irq */
s->irq_status &= ~value;
} else if (addr == TNETW1130_EE_START) {
if (value & 1) {
TRACE(TNETW, logout("start burst read from EEPROM\n"));
}
} else if (addr == TNETW1130_ECPU_CTRL) {
if (value & 1) {
TRACE(TNETW, logout("halt eCPU\n"));
//~ reg_write16(s->mem0, addr, value & ~1);
} else {
TRACE(TNETW, logout("start eCPU\n"));
s->irq_status |= HOST_INT_FCS_THRESHOLD;
}
}
TRACE(TNETW, logout("addr %s = 0x%04x\n", tnetw1130_regname(addr), value));
}
