t_stat clk_attach (UNIT *uptr, CONST char *cptr) { t_stat r; uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE); memset (uptr->filebuf, 0, (size_t)uptr->capac); r = attach_unit (uptr, cptr); if (r != SCPE_OK) uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); else { TOY *toy = (TOY *)uptr->filebuf; uptr->hwmark = (uint32) uptr->capac; if ((toy->toy_endian_plus2 < 2) || (toy->toy_endian_plus2 > 3)) memset (uptr->filebuf, 0, (size_t)uptr->capac); else { if (toy->toy_endian_plus2 != sim_end + 2) { /* wrong endian? */ toy->toy_gmtbase = sim_byteswap32 (toy->toy_gmtbase); toy->toy_gmtbasemsec = sim_byteswap32 (toy->toy_gmtbasemsec); } } toy->toy_endian_plus2 = sim_end + 2; todr_resync (); } return r; }
t_stat tmr_reset (DEVICE *dptr) { tmr_iccs = 0; tmr_nicr = 0; tmr_int = 0; sim_cancel (&tmr_unit); /* cancel timer */ todr_resync (); /* resync TODR */ return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ clk_unit.filebuf = calloc(sizeof(TOY), 1); if (clk_unit.filebuf == NULL) return SCPE_MEM; } todr_resync (); return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { int32 t; todr_resync (); /* resync clock */ clk_csr = 0; CLR_INT (CLK); t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */ sim_activate_abs (&clk_unit, t); /* activate unit */ tmr_poll = t; /* set tmr poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */ return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { sim_register_clock_unit (&clk_unit); /* declare clock unit */ tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */ sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */ tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ clk_unit.filebuf = calloc(sizeof(TOY), 1); if (clk_unit.filebuf == NULL) return SCPE_MEM; todr_resync (); } return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { int32 t; clk_csr = 0; CLR_INT (CLK); t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */ sim_activate_abs (&clk_unit, t); /* activate unit */ tmr_poll = t; /* set tmr poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */ if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ clk_unit.filebuf = calloc(sizeof(TOY), 1); if (clk_unit.filebuf == NULL) return SCPE_MEM; todr_resync (); } return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { int32 t; clk_csr = 0; CLR_INT (CLK); if (!sim_is_running) { /* RESET (not IORESET)? */ t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */ sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */ tmr_poll = t; /* set tmr poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */ } if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ clk_unit.filebuf = calloc(sizeof(TOY), 1); if (clk_unit.filebuf == NULL) return SCPE_MEM; todr_resync (); } return SCPE_OK; }