int
tws_init_ctlr(struct tws_softc *sc)
{
u_int64_t reg;
u_int32_t regh, regl;
TWS_TRACE_DEBUG(sc, "entry", sc, sc->is64bit);
sc->obfl_q_overrun = false;
if ( tws_init_connect(sc, tws_queue_depth) )
{
TWS_TRACE_DEBUG(sc, "initConnect failed", 0, sc->is64bit);
return(FAILURE);
}
while( 1 ) {
regh = tws_read_reg(sc, TWS_I2O0_IOPOBQPH, 4);
regl = tws_read_reg(sc, TWS_I2O0_IOPOBQPL, 4);
reg = (((u_int64_t)regh) << 32) | regl;
TWS_TRACE_DEBUG(sc, "host outbound cleanup",reg, regl);
if ( regh == TWS_FIFO_EMPTY32 )
break;
}
tws_init_obfl_q(sc);
tws_display_ctlr_info(sc);
tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4);
tws_turn_on_interrupts(sc);
return(SUCCESS);
}
static void
tws_reinit(void *arg)
{
struct tws_softc *sc = (struct tws_softc *)arg;
int timeout_val=0;
int try=2;
int done=0;
// device_printf(sc->tws_dev, "Waiting for Controller Ready\n");
while ( !done && try ) {
if ( tws_ctlr_ready(sc) ) {
done = 1;
break;
} else {
timeout_val += 5;
if ( timeout_val >= TWS_RESET_TIMEOUT ) {
timeout_val = 0;
if ( try )
tws_assert_soft_reset(sc);
try--;
}
mtx_sleep(sc, &sc->gen_lock, 0, "tws_reinit", 5*hz);
}
}
if (!done) {
device_printf(sc->tws_dev, "FAILED to get Controller Ready!\n");
return;
}
sc->obfl_q_overrun = false;
// device_printf(sc->tws_dev, "Sending initConnect\n");
if ( tws_init_connect(sc, tws_queue_depth) ) {
TWS_TRACE_DEBUG(sc, "initConnect failed", 0, sc->is64bit);
}
tws_init_obfl_q(sc);
tws_turn_on_interrupts(sc);
wakeup_one(sc);
}