bool vl_compositor_init(struct vl_compositor *c, struct pipe_context *pipe) { assert(c); memset(c, 0, sizeof(*c)); c->pipe = pipe; c->upload = u_upload_create(pipe, 128 * 1024, 4, PIPE_BIND_VERTEX_BUFFER); if (!c->upload) return false; if (!init_pipe_state(c)) { u_upload_destroy(c->upload); return false; } if (!init_shaders(c)) { u_upload_destroy(c->upload); cleanup_pipe_state(c); return false; } if (!init_buffers(c)) { u_upload_destroy(c->upload); cleanup_shaders(c); cleanup_pipe_state(c); return false; } return true; }
struct pipe_context * vc4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) { struct vc4_screen *screen = vc4_screen(pscreen); struct vc4_context *vc4; /* Prevent dumping of the shaders built during context setup. */ uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB; vc4_debug &= ~VC4_DEBUG_SHADERDB; vc4 = rzalloc(NULL, struct vc4_context); if (!vc4) return NULL; struct pipe_context *pctx = &vc4->base; vc4->screen = screen; pctx->screen = pscreen; pctx->priv = priv; pctx->destroy = vc4_context_destroy; pctx->flush = vc4_pipe_flush; pctx->invalidate_resource = vc4_invalidate_resource; vc4_draw_init(pctx); vc4_state_init(pctx); vc4_program_init(pctx); vc4_query_init(pctx); vc4_resource_context_init(pctx); vc4_job_init(vc4); vc4->fd = screen->fd; util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer), 16, UTIL_SLAB_SINGLETHREADED); vc4->blitter = util_blitter_create(pctx); if (!vc4->blitter) goto fail; vc4->primconvert = util_primconvert_create(pctx, (1 << PIPE_PRIM_QUADS) - 1); if (!vc4->primconvert) goto fail; vc4->uploader = u_upload_create(pctx, 16 * 1024, PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM); vc4_debug |= saved_shaderdb_flag; vc4->sample_mask = (1 << VC4_MAX_SAMPLES) - 1; return &vc4->base; fail: pctx->destroy(pctx); return NULL; }
struct u_upload_mgr * u_upload_create_default(struct pipe_context *pipe) { return u_upload_create(pipe, 1024 * 1024, PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER | PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM, 0); }
bool r600_common_context_init(struct r600_common_context *rctx, struct r600_common_screen *rscreen) { util_slab_create(&rctx->pool_transfers, sizeof(struct r600_transfer), 64, UTIL_SLAB_SINGLETHREADED); rctx->screen = rscreen; rctx->ws = rscreen->ws; rctx->family = rscreen->family; rctx->chip_class = rscreen->chip_class; if (rscreen->family == CHIP_HAWAII) rctx->max_db = 16; else if (rscreen->chip_class >= EVERGREEN) rctx->max_db = 8; else rctx->max_db = 4; rctx->b.transfer_map = u_transfer_map_vtbl; rctx->b.transfer_flush_region = u_default_transfer_flush_region; rctx->b.transfer_unmap = u_transfer_unmap_vtbl; rctx->b.transfer_inline_write = u_default_transfer_inline_write; rctx->b.memory_barrier = r600_memory_barrier; rctx->b.flush = r600_flush_from_st; LIST_INITHEAD(&rctx->texture_buffers); r600_init_context_texture_functions(rctx); r600_streamout_init(rctx); r600_query_init(rctx); cayman_init_msaa(&rctx->b); rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4, 0, PIPE_USAGE_DEFAULT, TRUE); if (!rctx->allocator_so_filled_size) return false; rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256, PIPE_BIND_INDEX_BUFFER | PIPE_BIND_CONSTANT_BUFFER); if (!rctx->uploader) return false; if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) { rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA, r600_flush_dma_ring, rctx, NULL); rctx->rings.dma.flush = r600_flush_dma_ring; } return true; }
struct u_upload_mgr * u_upload_clone(struct pipe_context *pipe, struct u_upload_mgr *upload) { struct u_upload_mgr *result = u_upload_create(pipe, upload->default_size, upload->bind, upload->usage, upload->flags); if (upload->map_persistent && upload->map_flags & PIPE_TRANSFER_FLUSH_EXPLICIT) u_upload_enable_flush_explicit(result); return result; }
struct pipe_context * fd4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) { struct fd_screen *screen = fd_screen(pscreen); struct fd4_context *fd4_ctx = CALLOC_STRUCT(fd4_context); struct pipe_context *pctx; if (!fd4_ctx) return NULL; pctx = &fd4_ctx->base.base; pctx->screen = pscreen; fd4_ctx->base.dev = fd_device_ref(screen->dev); fd4_ctx->base.screen = fd_screen(pscreen); pctx->destroy = fd4_context_destroy; pctx->create_blend_state = fd4_blend_state_create; pctx->create_rasterizer_state = fd4_rasterizer_state_create; pctx->create_depth_stencil_alpha_state = fd4_zsa_state_create; fd4_draw_init(pctx); fd4_gmem_init(pctx); fd4_texture_init(pctx); fd4_prog_init(pctx); fd4_emit_init(pctx); pctx = fd_context_init(&fd4_ctx->base, pscreen, primtypes, priv, flags); if (!pctx) return NULL; fd_hw_query_init(pctx); fd4_ctx->vs_pvt_mem = fd_bo_new(screen->dev, 0x2000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vs_pvt"); fd4_ctx->fs_pvt_mem = fd_bo_new(screen->dev, 0x2000, DRM_FREEDRENO_GEM_TYPE_KMEM, "fs_pvt"); fd4_ctx->vsc_size_mem = fd_bo_new(screen->dev, 0x1000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_size"); fd_context_setup_common_vbos(&fd4_ctx->base); fd4_query_context_init(pctx); fd4_ctx->border_color_uploader = u_upload_create(pctx, 4096, 0, PIPE_USAGE_STREAM, 0); return pctx; }
struct u_vbuf * u_vbuf_create(struct pipe_context *pipe, struct u_vbuf_caps *caps) { struct u_vbuf *mgr = CALLOC_STRUCT(u_vbuf); mgr->caps = *caps; mgr->pipe = pipe; mgr->cso_cache = cso_cache_create(); mgr->translate_cache = translate_cache_create(); memset(mgr->fallback_vbs, ~0, sizeof(mgr->fallback_vbs)); mgr->uploader = u_upload_create(pipe, 1024 * 1024, 4, PIPE_BIND_VERTEX_BUFFER); return mgr; }
struct u_vbuf * u_vbuf_create(struct pipe_context *pipe, unsigned upload_buffer_size, unsigned upload_buffer_alignment, unsigned upload_buffer_bind, enum u_fetch_alignment fetch_alignment) { struct u_vbuf_priv *mgr = CALLOC_STRUCT(u_vbuf_priv); mgr->pipe = pipe; mgr->translate_cache = translate_cache_create(); mgr->fallback_vb_slot = ~0; mgr->b.uploader = u_upload_create(pipe, upload_buffer_size, upload_buffer_alignment, upload_buffer_bind); mgr->b.caps.fetch_dword_unaligned = fetch_alignment == U_VERTEX_FETCH_BYTE_ALIGNED; u_vbuf_init_format_caps(mgr); return &mgr->b; }
/** * Create a context. * * This is where each context begins. */ struct pipe_context * iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags) { struct iris_screen *screen = (struct iris_screen*)pscreen; const struct gen_device_info *devinfo = &screen->devinfo; struct iris_context *ice = rzalloc(NULL, struct iris_context); if (!ice) return NULL; struct pipe_context *ctx = &ice->ctx; ctx->screen = pscreen; ctx->priv = priv; ctx->stream_uploader = u_upload_create_default(ctx); if (!ctx->stream_uploader) { free(ctx); return NULL; } ctx->const_uploader = ctx->stream_uploader; ctx->destroy = iris_destroy_context; ctx->set_debug_callback = iris_set_debug_callback; ctx->set_device_reset_callback = iris_set_device_reset_callback; ctx->get_device_reset_status = iris_get_device_reset_status; ctx->get_sample_position = iris_get_sample_position; ice->shaders.urb_size = devinfo->urb.size; iris_init_context_fence_functions(ctx); iris_init_blit_functions(ctx); iris_init_clear_functions(ctx); iris_init_program_functions(ctx); iris_init_resource_functions(ctx); iris_init_query_functions(ctx); iris_init_flush_functions(ctx); iris_init_program_cache(ice); iris_init_border_color_pool(ice); iris_init_binder(ice); slab_create_child(&ice->transfer_pool, &screen->transfer_pool); ice->state.surface_uploader = u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, IRIS_RESOURCE_FLAG_SURFACE_MEMZONE); ice->state.dynamic_uploader = u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE); ice->query_buffer_uploader = u_upload_create(ctx, 4096, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, 0); genX_call(devinfo, init_state, ice); genX_call(devinfo, init_blorp, ice); int priority = 0; if (flags & PIPE_CONTEXT_HIGH_PRIORITY) priority = GEN_CONTEXT_HIGH_PRIORITY; if (flags & PIPE_CONTEXT_LOW_PRIORITY) priority = GEN_CONTEXT_LOW_PRIORITY; if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) ice->state.sizes = _mesa_hash_table_u64_create(ice); for (int i = 0; i < IRIS_BATCH_COUNT; i++) { iris_init_batch(&ice->batches[i], screen, &ice->vtbl, &ice->dbg, &ice->reset, ice->state.sizes, ice->batches, (enum iris_batch_name) i, I915_EXEC_RENDER, priority); } ice->vtbl.init_render_context(screen, &ice->batches[IRIS_BATCH_RENDER], &ice->vtbl, &ice->dbg); ice->vtbl.init_compute_context(screen, &ice->batches[IRIS_BATCH_COMPUTE], &ice->vtbl, &ice->dbg); return ctx; }
struct pipe_context* r300_create_context(struct pipe_screen* screen, void *priv) { struct r300_context* r300 = CALLOC_STRUCT(r300_context); struct r300_screen* r300screen = r300_screen(screen); struct radeon_winsys *rws = r300screen->rws; if (!r300) return NULL; r300->rws = rws; r300->screen = r300screen; r300->context.screen = screen; r300->context.priv = priv; r300->context.destroy = r300_destroy_context; util_slab_create(&r300->pool_transfers, sizeof(struct pipe_transfer), 64, UTIL_SLAB_SINGLETHREADED); r300->cs = rws->cs_create(rws, RING_GFX, r300_flush_callback, r300, NULL); if (r300->cs == NULL) goto fail; if (!r300screen->caps.has_tcl) { /* Create a Draw. This is used for SW TCL. */ r300->draw = draw_create(&r300->context); if (r300->draw == NULL) goto fail; /* Enable our renderer. */ draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300)); /* Disable converting points/lines to triangles. */ draw_wide_line_threshold(r300->draw, 10000000.f); draw_wide_point_threshold(r300->draw, 10000000.f); draw_wide_point_sprites(r300->draw, FALSE); draw_enable_line_stipple(r300->draw, TRUE); draw_enable_point_sprites(r300->draw, FALSE); } if (!r300_setup_atoms(r300)) goto fail; r300_init_blit_functions(r300); r300_init_flush_functions(r300); r300_init_query_functions(r300); r300_init_state_functions(r300); r300_init_resource_functions(r300); r300_init_render_functions(r300); r300_init_states(&r300->context); r300->context.create_video_codec = vl_create_decoder; r300->context.create_video_buffer = vl_video_buffer_create; r300->uploader = u_upload_create(&r300->context, 256 * 1024, 4, PIPE_BIND_CUSTOM); r300->blitter = util_blitter_create(&r300->context); if (r300->blitter == NULL) goto fail; r300->blitter->draw_rectangle = r300_blitter_draw_rectangle; /* The KIL opcode needs the first texture unit to be enabled * on r3xx-r4xx. In order to calm down the CS checker, we bind this * dummy texture there. */ if (!r300->screen->caps.is_r500) { struct pipe_resource *tex; struct pipe_resource rtempl = {{0}}; struct pipe_sampler_view vtempl = {{0}}; rtempl.target = PIPE_TEXTURE_2D; rtempl.format = PIPE_FORMAT_I8_UNORM; rtempl.usage = PIPE_USAGE_IMMUTABLE; rtempl.width0 = 1; rtempl.height0 = 1; rtempl.depth0 = 1; tex = screen->resource_create(screen, &rtempl); u_sampler_view_default_template(&vtempl, tex, tex->format); r300->texkill_sampler = (struct r300_sampler_view*) r300->context.create_sampler_view(&r300->context, tex, &vtempl); pipe_resource_reference(&tex, NULL); } if (r300screen->caps.has_tcl) { struct pipe_resource vb; memset(&vb, 0, sizeof(vb)); vb.target = PIPE_BUFFER; vb.format = PIPE_FORMAT_R8_UNORM; vb.usage = PIPE_USAGE_DEFAULT; vb.width0 = sizeof(float) * 16; vb.height0 = 1; vb.depth0 = 1; r300->dummy_vb.buffer = screen->resource_create(screen, &vb); r300->context.set_vertex_buffers(&r300->context, 0, 1, &r300->dummy_vb); } { struct pipe_depth_stencil_alpha_state dsa; memset(&dsa, 0, sizeof(dsa)); dsa.depth.writemask = 1; r300->dsa_decompress_zmask = r300->context.create_depth_stencil_alpha_state(&r300->context, &dsa); } r300->hyperz_time_of_last_flush = os_time_get(); /* Register allocator state */ rc_init_regalloc_state(&r300->fs_regalloc_state); /* Print driver info. */ #ifdef DEBUG { #else if (DBG_ON(r300, DBG_INFO)) { #endif fprintf(stderr, "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n" "r300: GART size: %"PRIu64" MB, VRAM size: %"PRIu64" MB\n" "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n", r300->screen->info.drm_major, r300->screen->info.drm_minor, r300->screen->info.drm_patchlevel, screen->get_name(screen), r300->screen->info.pci_id, r300->screen->info.r300_num_gb_pipes, r300->screen->info.r300_num_z_pipes, r300->screen->info.gart_size >> 20, r300->screen->info.vram_size >> 20, "YES", /* XXX really? */ r300->screen->caps.zmask_ram ? "YES" : "NO", r300->screen->caps.hiz_ram ? "YES" : "NO"); } return &r300->context; fail: r300_destroy_context(&r300->context); return NULL; }
static struct st_context * st_create_context_priv( struct gl_context *ctx, struct pipe_context *pipe, const struct st_config_options *options) { struct pipe_screen *screen = pipe->screen; uint i; struct st_context *st = ST_CALLOC_STRUCT( st_context ); st->options = *options; ctx->st = st; st->ctx = ctx; st->pipe = pipe; /* XXX: this is one-off, per-screen init: */ st_debug_init(); /* state tracker needs the VBO module */ _vbo_CreateContext(ctx); st->dirty.mesa = ~0; st->dirty.st = ~0; /* Create upload manager for vertex data for glBitmap, glDrawPixels, * glClear, etc. */ st->uploader = u_upload_create(st->pipe, 65536, PIPE_BIND_VERTEX_BUFFER, PIPE_USAGE_STREAM); if (!screen->get_param(screen, PIPE_CAP_USER_INDEX_BUFFERS)) { st->indexbuf_uploader = u_upload_create(st->pipe, 128 * 1024, PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM); } if (!screen->get_param(screen, PIPE_CAP_USER_CONSTANT_BUFFERS)) st->constbuf_uploader = u_upload_create(pipe, 128 * 1024, PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM); st->cso_context = cso_create_context(pipe); st_init_atoms( st ); st_init_bitmap(st); st_init_clear(st); st_init_draw( st ); /* Choose texture target for glDrawPixels, glBitmap, renderbuffers */ if (pipe->screen->get_param(pipe->screen, PIPE_CAP_NPOT_TEXTURES)) st->internal_target = PIPE_TEXTURE_2D; else st->internal_target = PIPE_TEXTURE_RECT; /* Vertex element objects used for drawing rectangles for glBitmap, * glDrawPixels, glClear, etc. */ for (i = 0; i < ARRAY_SIZE(st->velems_util_draw); i++) { memset(&st->velems_util_draw[i], 0, sizeof(struct pipe_vertex_element)); st->velems_util_draw[i].src_offset = i * 4 * sizeof(float); st->velems_util_draw[i].instance_divisor = 0; st->velems_util_draw[i].vertex_buffer_index = cso_get_aux_vertex_buffer_slot(st->cso_context); st->velems_util_draw[i].src_format = PIPE_FORMAT_R32G32B32A32_FLOAT; } /* we want all vertex data to be placed in buffer objects */ vbo_use_buffer_objects(ctx); /* make sure that no VBOs are left mapped when we're drawing. */ vbo_always_unmap_buffers(ctx); /* Need these flags: */ st->ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; st->ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; st->has_stencil_export = screen->get_param(screen, PIPE_CAP_SHADER_STENCIL_EXPORT); st->has_shader_model3 = screen->get_param(screen, PIPE_CAP_SM3); st->has_etc1 = screen->is_format_supported(screen, PIPE_FORMAT_ETC1_RGB8, PIPE_TEXTURE_2D, 0, PIPE_BIND_SAMPLER_VIEW); st->has_etc2 = screen->is_format_supported(screen, PIPE_FORMAT_ETC2_RGB8, PIPE_TEXTURE_2D, 0, PIPE_BIND_SAMPLER_VIEW); st->prefer_blit_based_texture_transfer = screen->get_param(screen, PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER); st->force_persample_in_shader = screen->get_param(screen, PIPE_CAP_SAMPLE_SHADING) && !screen->get_param(screen, PIPE_CAP_FORCE_PERSAMPLE_INTERP); st->has_shareable_shaders = screen->get_param(screen, PIPE_CAP_SHAREABLE_SHADERS); st->needs_texcoord_semantic = screen->get_param(screen, PIPE_CAP_TGSI_TEXCOORD); st->apply_texture_swizzle_to_border_color = !!(screen->get_param(screen, PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK) & (PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 | PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600)); st->has_time_elapsed = screen->get_param(screen, PIPE_CAP_QUERY_TIME_ELAPSED); st->has_half_float_packing = screen->get_param(screen, PIPE_CAP_TGSI_PACK_HALF_FLOAT); st->has_multi_draw_indirect = screen->get_param(screen, PIPE_CAP_MULTI_DRAW_INDIRECT); /* GL limits and extensions */ st_init_limits(st->pipe->screen, &ctx->Const, &ctx->Extensions); st_init_extensions(st->pipe->screen, &ctx->Const, &ctx->Extensions, &st->options, ctx->Mesa_DXTn); if (st_have_perfmon(st)) { ctx->Extensions.AMD_performance_monitor = GL_TRUE; } /* Enable shader-based fallbacks for ARB_color_buffer_float if needed. */ if (screen->get_param(screen, PIPE_CAP_VERTEX_COLOR_UNCLAMPED)) { if (!screen->get_param(screen, PIPE_CAP_VERTEX_COLOR_CLAMPED)) { st->clamp_vert_color_in_shader = GL_TRUE; } if (!screen->get_param(screen, PIPE_CAP_FRAGMENT_COLOR_CLAMPED)) { st->clamp_frag_color_in_shader = GL_TRUE; } /* For drivers which cannot do color clamping, it's better to just * disable ARB_color_buffer_float in the core profile, because * the clamping is deprecated there anyway. */ if (ctx->API == API_OPENGL_CORE && (st->clamp_frag_color_in_shader || st->clamp_vert_color_in_shader)) { st->clamp_vert_color_in_shader = GL_FALSE; st->clamp_frag_color_in_shader = GL_FALSE; ctx->Extensions.ARB_color_buffer_float = GL_FALSE; } } /* called after _mesa_create_context/_mesa_init_point, fix default user * settable max point size up */ st->ctx->Point.MaxSize = MAX2(ctx->Const.MaxPointSize, ctx->Const.MaxPointSizeAA); /* For vertex shaders, make sure not to emit saturate when SM 3.0 is not supported */ ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitNoSat = !st->has_shader_model3; if (!ctx->Extensions.ARB_gpu_shader5) { for (i = 0; i < MESA_SHADER_STAGES; i++) ctx->Const.ShaderCompilerOptions[i].EmitNoIndirectSampler = true; } /* Set which shader types can be compiled at link time. */ st->shader_has_one_variant[MESA_SHADER_VERTEX] = st->has_shareable_shaders && !st->clamp_vert_color_in_shader; st->shader_has_one_variant[MESA_SHADER_FRAGMENT] = st->has_shareable_shaders && !st->clamp_frag_color_in_shader && !st->force_persample_in_shader; st->shader_has_one_variant[MESA_SHADER_TESS_CTRL] = st->has_shareable_shaders; st->shader_has_one_variant[MESA_SHADER_TESS_EVAL] = st->has_shareable_shaders; st->shader_has_one_variant[MESA_SHADER_GEOMETRY] = st->has_shareable_shaders; _mesa_compute_version(ctx); if (ctx->Version == 0) { /* This can happen when a core profile was requested, but the driver * does not support some features of GL 3.1 or later. */ st_destroy_context_priv(st); return NULL; } _mesa_initialize_dispatch_tables(ctx); _mesa_initialize_vbo_vtxfmt(ctx); return st; }
bool r600_common_context_init(struct r600_common_context *rctx, struct r600_common_screen *rscreen) { util_slab_create(&rctx->pool_transfers, sizeof(struct r600_transfer), 64, UTIL_SLAB_SINGLETHREADED); rctx->screen = rscreen; rctx->ws = rscreen->ws; rctx->family = rscreen->family; rctx->chip_class = rscreen->chip_class; if (rscreen->chip_class >= CIK) rctx->max_db = MAX2(8, rscreen->info.r600_num_backends); else if (rscreen->chip_class >= EVERGREEN) rctx->max_db = 8; else rctx->max_db = 4; rctx->b.invalidate_resource = r600_invalidate_resource; rctx->b.transfer_map = u_transfer_map_vtbl; rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl; rctx->b.transfer_unmap = u_transfer_unmap_vtbl; rctx->b.transfer_inline_write = u_default_transfer_inline_write; rctx->b.memory_barrier = r600_memory_barrier; rctx->b.flush = r600_flush_from_st; rctx->b.set_debug_callback = r600_set_debug_callback; if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) { rctx->b.get_device_reset_status = r600_get_reset_status; rctx->gpu_reset_counter = rctx->ws->query_value(rctx->ws, RADEON_GPU_RESET_COUNTER); } LIST_INITHEAD(&rctx->texture_buffers); r600_init_context_texture_functions(rctx); r600_streamout_init(rctx); r600_query_init(rctx); cayman_init_msaa(&rctx->b); rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4, 0, PIPE_USAGE_DEFAULT, TRUE); if (!rctx->allocator_so_filled_size) return false; rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, PIPE_BIND_INDEX_BUFFER | PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM); if (!rctx->uploader) return false; rctx->ctx = rctx->ws->ctx_create(rctx->ws); if (!rctx->ctx) return false; if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) { rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA, r600_flush_dma_ring, rctx, NULL); rctx->dma.flush = r600_flush_dma_ring; } return true; }
.src_format = PIPE_FORMAT_R32G32B32_FLOAT, }}); fd4_ctx->solid_vbuf_state.vertexbuf.count = 1; fd4_ctx->solid_vbuf_state.vertexbuf.vb[0].stride = 12; fd4_ctx->solid_vbuf_state.vertexbuf.vb[0].buffer = fd4_ctx->solid_vbuf; /* setup blit_vbuf_state: */ fd4_ctx->blit_vbuf_state.vtx = pctx->create_vertex_elements_state( pctx, 2, (struct pipe_vertex_element[]){{ .vertex_buffer_index = 0, .src_offset = 0, .src_format = PIPE_FORMAT_R32G32_FLOAT, }, { .vertex_buffer_index = 1, .src_offset = 0, .src_format = PIPE_FORMAT_R32G32B32_FLOAT, }}); fd4_ctx->blit_vbuf_state.vertexbuf.count = 2; fd4_ctx->blit_vbuf_state.vertexbuf.vb[0].stride = 8; fd4_ctx->blit_vbuf_state.vertexbuf.vb[0].buffer = fd4_ctx->blit_texcoord_vbuf; fd4_ctx->blit_vbuf_state.vertexbuf.vb[1].stride = 12; fd4_ctx->blit_vbuf_state.vertexbuf.vb[1].buffer = fd4_ctx->solid_vbuf; fd4_query_context_init(pctx); fd4_ctx->border_color_uploader = u_upload_create(pctx, 4096, 0, PIPE_USAGE_STREAM); return pctx; }
static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags) { struct si_context *sctx = CALLOC_STRUCT(si_context); struct si_screen* sscreen = (struct si_screen *)screen; struct radeon_winsys *ws = sscreen->ws; int shader, i; bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0; if (!sctx) return NULL; sctx->has_graphics = sscreen->info.chip_class == SI || !(flags & PIPE_CONTEXT_COMPUTE_ONLY); if (flags & PIPE_CONTEXT_DEBUG) sscreen->record_llvm_ir = true; /* racy but not critical */ sctx->b.screen = screen; /* this must be set first */ sctx->b.priv = NULL; sctx->b.destroy = si_destroy_context; sctx->screen = sscreen; /* Easy accessing of screen/winsys. */ sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0; slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers); slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers); sctx->ws = sscreen->ws; sctx->family = sscreen->info.family; sctx->chip_class = sscreen->info.chip_class; if (sscreen->info.has_gpu_reset_counter_query) { sctx->gpu_reset_counter = sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER); } if (sctx->chip_class == CIK || sctx->chip_class == VI || sctx->chip_class == GFX9) { sctx->eop_bug_scratch = si_resource( pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 16 * sscreen->info.num_render_backends)); if (!sctx->eop_bug_scratch) goto fail; } /* Initialize context allocators. */ sctx->allocator_zeroed_memory = u_suballocator_create(&sctx->b, 128 * 1024, 0, PIPE_USAGE_DEFAULT, SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_CLEAR, false); if (!sctx->allocator_zeroed_memory) goto fail; sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024, 0, PIPE_USAGE_STREAM, SI_RESOURCE_FLAG_READ_ONLY); if (!sctx->b.stream_uploader) goto fail; sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024, 0, PIPE_USAGE_STAGING, 0); if (!sctx->cached_gtt_allocator) goto fail; sctx->ctx = sctx->ws->ctx_create(sctx->ws); if (!sctx->ctx) goto fail; if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) { sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA, (void*)si_flush_dma_cs, sctx, stop_exec_on_failure); } bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs; sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024, 0, PIPE_USAGE_DEFAULT, SI_RESOURCE_FLAG_32BIT | (use_sdma_upload ? SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : (sscreen->cpdma_prefetch_writes_memory ? 0 : SI_RESOURCE_FLAG_READ_ONLY))); if (!sctx->b.const_uploader) goto fail; if (use_sdma_upload) u_upload_enable_flush_explicit(sctx->b.const_uploader); sctx->gfx_cs = ws->cs_create(sctx->ctx, sctx->has_graphics ? RING_GFX : RING_COMPUTE, (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure); /* Border colors. */ sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)); if (!sctx->border_color_table) goto fail; sctx->border_color_buffer = si_resource( pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table))); if (!sctx->border_color_buffer) goto fail; sctx->border_color_map = ws->buffer_map(sctx->border_color_buffer->buf, NULL, PIPE_TRANSFER_WRITE); if (!sctx->border_color_map) goto fail; /* Initialize context functions used by graphics and compute. */ sctx->b.emit_string_marker = si_emit_string_marker; sctx->b.set_debug_callback = si_set_debug_callback; sctx->b.set_log_context = si_set_log_context; sctx->b.set_context_param = si_set_context_param; sctx->b.get_device_reset_status = si_get_reset_status; sctx->b.set_device_reset_callback = si_set_device_reset_callback; si_init_all_descriptors(sctx); si_init_buffer_functions(sctx); si_init_clear_functions(sctx); si_init_blit_functions(sctx); si_init_compute_functions(sctx); si_init_compute_blit_functions(sctx); si_init_debug_functions(sctx); si_init_fence_functions(sctx); si_init_state_compute_functions(sctx); if (sscreen->debug_flags & DBG(FORCE_DMA)) sctx->b.resource_copy_region = sctx->dma_copy; /* Initialize graphics-only context functions. */ if (sctx->has_graphics) { si_init_context_texture_functions(sctx); si_init_query_functions(sctx); si_init_msaa_functions(sctx); si_init_shader_functions(sctx); si_init_state_functions(sctx); si_init_streamout_functions(sctx); si_init_viewport_functions(sctx); sctx->blitter = util_blitter_create(&sctx->b); if (sctx->blitter == NULL) goto fail; sctx->blitter->skip_viewport_restore = true; si_init_draw_functions(sctx); } /* Initialize SDMA functions. */ if (sctx->chip_class >= CIK) cik_init_sdma_functions(sctx); else si_init_dma_functions(sctx); sctx->sample_mask = 0xffff; /* Initialize multimedia functions. */ if (sscreen->info.has_hw_decode) { sctx->b.create_video_codec = si_uvd_create_decoder; sctx->b.create_video_buffer = si_video_buffer_create; } else { sctx->b.create_video_codec = vl_create_decoder; sctx->b.create_video_buffer = vl_video_buffer_create; } if (sctx->chip_class >= GFX9) { sctx->wait_mem_scratch = si_resource( pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4)); if (!sctx->wait_mem_scratch) goto fail; /* Initialize the memory. */ si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, V_370_MEM, V_370_ME, &sctx->wait_mem_number); } /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */ if (sctx->chip_class == CIK) { sctx->null_const_buf.buffer = pipe_aligned_buffer_create(screen, SI_RESOURCE_FLAG_32BIT, PIPE_USAGE_DEFAULT, 16, sctx->screen->info.tcc_cache_line_size); if (!sctx->null_const_buf.buffer) goto fail; sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0; unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE; for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) { for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) { sctx->b.set_constant_buffer(&sctx->b, shader, i, &sctx->null_const_buf); } } si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &sctx->null_const_buf); si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &sctx->null_const_buf); si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &sctx->null_const_buf); si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &sctx->null_const_buf); si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &sctx->null_const_buf); } uint64_t max_threads_per_block; screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI, PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, &max_threads_per_block); /* The maximum number of scratch waves. Scratch space isn't divided * evenly between CUs. The number is only a function of the number of CUs. * We can decrease the constant to decrease the scratch buffer size. * * sctx->scratch_waves must be >= the maximum posible size of * 1 threadgroup, so that the hw doesn't hang from being unable * to start any. * * The recommended value is 4 per CU at most. Higher numbers don't * bring much benefit, but they still occupy chip resources (think * async compute). I've seen ~2% performance difference between 4 and 32. */ sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units, max_threads_per_block / 64); si_init_compiler(sscreen, &sctx->compiler); /* Bindless handles. */ sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal); sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal); util_dynarray_init(&sctx->resident_tex_handles, NULL); util_dynarray_init(&sctx->resident_img_handles, NULL); util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL); util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL); util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL); sctx->sample_pos_buffer = pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT, sizeof(sctx->sample_positions)); pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0, sizeof(sctx->sample_positions), &sctx->sample_positions); /* this must be last */ si_begin_new_gfx_cs(sctx); if (sctx->chip_class == CIK) { /* Clear the NULL constant buffer, because loads should return zeros. * Note that this forces CP DMA to be used, because clover deadlocks * for some reason when the compute codepath is used. */ uint32_t clear_value = 0; si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0, &clear_value, 4, SI_COHERENCY_SHADER, true); } return &sctx->b; fail: fprintf(stderr, "radeonsi: Failed to create a context.\n"); si_destroy_context(&sctx->b); return NULL; }
struct pipe_context *svga_context_create( struct pipe_screen *screen, void *priv ) { struct svga_screen *svgascreen = svga_screen(screen); struct svga_context *svga = NULL; enum pipe_error ret; svga = CALLOC_STRUCT(svga_context); if (svga == NULL) goto no_svga; svga->pipe.screen = screen; svga->pipe.priv = priv; svga->pipe.destroy = svga_destroy; svga->pipe.clear = svga_clear; svga->swc = svgascreen->sws->context_create(svgascreen->sws); if(!svga->swc) goto no_swc; svga_init_resource_functions(svga); svga_init_blend_functions(svga); svga_init_blit_functions(svga); svga_init_depth_stencil_functions(svga); svga_init_draw_functions(svga); svga_init_flush_functions(svga); svga_init_misc_functions(svga); svga_init_rasterizer_functions(svga); svga_init_sampler_functions(svga); svga_init_fs_functions(svga); svga_init_vs_functions(svga); svga_init_vertex_functions(svga); svga_init_constbuffer_functions(svga); svga_init_query_functions(svga); svga_init_surface_functions(svga); /* debug */ svga->debug.no_swtnl = debug_get_option_no_swtnl(); svga->debug.force_swtnl = debug_get_option_force_swtnl(); svga->debug.use_min_mipmap = debug_get_option_use_min_mipmap(); svga->debug.disable_shader = debug_get_option_disable_shader(); svga->debug.no_line_width = debug_get_option_no_line_width(); svga->debug.force_hw_line_stipple = debug_get_option_force_hw_line_stipple(); svga->fs_bm = util_bitmask_create(); if (svga->fs_bm == NULL) goto no_fs_bm; svga->vs_bm = util_bitmask_create(); if (svga->vs_bm == NULL) goto no_vs_bm; svga->upload_ib = u_upload_create( &svga->pipe, 32 * 1024, 16, PIPE_BIND_INDEX_BUFFER ); if (svga->upload_ib == NULL) goto no_upload_ib; svga->upload_vb = u_upload_create( &svga->pipe, 128 * 1024, 16, PIPE_BIND_VERTEX_BUFFER ); if (svga->upload_vb == NULL) goto no_upload_vb; svga->hwtnl = svga_hwtnl_create( svga, svga->upload_ib, svga->swc ); if (svga->hwtnl == NULL) goto no_hwtnl; if (!svga_init_swtnl(svga)) goto no_swtnl; ret = svga_emit_initial_state( svga ); if (ret != PIPE_OK) goto no_state; /* Avoid shortcircuiting state with initial value of zero. */ memset(&svga->state.hw_clear, 0xcd, sizeof(svga->state.hw_clear)); memset(&svga->state.hw_clear.framebuffer, 0x0, sizeof(svga->state.hw_clear.framebuffer)); memset(&svga->state.hw_draw, 0xcd, sizeof(svga->state.hw_draw)); memset(&svga->state.hw_draw.views, 0x0, sizeof(svga->state.hw_draw.views)); svga->state.hw_draw.num_views = 0; svga->dirty = ~0; LIST_INITHEAD(&svga->dirty_buffers); return &svga->pipe; no_state: svga_destroy_swtnl(svga); no_swtnl: svga_hwtnl_destroy( svga->hwtnl ); no_hwtnl: u_upload_destroy( svga->upload_vb ); no_upload_vb: u_upload_destroy( svga->upload_ib ); no_upload_ib: util_bitmask_destroy( svga->vs_bm ); no_vs_bm: util_bitmask_destroy( svga->fs_bm ); no_fs_bm: svga->swc->destroy(svga->swc); no_swc: FREE(svga); no_svga: return NULL; }
static struct pipe_context * ilo_context_create(struct pipe_screen *screen, void *priv, unsigned flags) { struct ilo_screen *is = ilo_screen(screen); struct ilo_context *ilo; ilo = CALLOC_STRUCT(ilo_context); if (!ilo) return NULL; ilo->winsys = is->dev.winsys; ilo->dev = &is->dev; /* * initialize first, otherwise it may not be safe to call * ilo_context_destroy() on errors */ slab_create(&ilo->transfer_mempool, sizeof(struct ilo_transfer), 64); ilo->shader_cache = ilo_shader_cache_create(); ilo->cp = ilo_cp_create(ilo->dev, ilo->winsys, ilo->shader_cache); if (ilo->cp) ilo->render = ilo_render_create(&ilo->cp->builder); if (!ilo->cp || !ilo->shader_cache || !ilo->render) { ilo_context_destroy(&ilo->base); return NULL; } ilo_cp_set_submit_callback(ilo->cp, ilo_context_cp_submitted, (void *) ilo); ilo->base.screen = screen; ilo->base.priv = priv; ilo->base.destroy = ilo_context_destroy; ilo->base.flush = ilo_flush; ilo->base.render_condition = ilo_render_condition; ilo_init_draw_functions(ilo); ilo_init_query_functions(ilo); ilo_init_state_functions(ilo); ilo_init_blit_functions(ilo); ilo_init_transfer_functions(ilo); ilo_init_video_functions(ilo); ilo_init_gpgpu_functions(ilo); ilo_init_draw(ilo); ilo_state_vector_init(ilo->dev, &ilo->state_vector); /* * These must be called last as u_upload/u_blitter are clients of the pipe * context. */ ilo->uploader = u_upload_create(&ilo->base, 1024 * 1024, PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM); if (!ilo->uploader) { ilo_context_destroy(&ilo->base); return NULL; } ilo->blitter = ilo_blitter_create(ilo); if (!ilo->blitter) { ilo_context_destroy(&ilo->base); return NULL; } return &ilo->base; }
struct pipe_context *svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags) { struct svga_screen *svgascreen = svga_screen(screen); struct svga_context *svga = NULL; enum pipe_error ret; svga = CALLOC_STRUCT(svga_context); if (!svga) goto cleanup; LIST_INITHEAD(&svga->dirty_buffers); svga->pipe.screen = screen; svga->pipe.priv = priv; svga->pipe.destroy = svga_destroy; svga->pipe.clear = svga_clear; svga->swc = svgascreen->sws->context_create(svgascreen->sws); if (!svga->swc) goto cleanup; svga_init_resource_functions(svga); svga_init_blend_functions(svga); svga_init_blit_functions(svga); svga_init_depth_stencil_functions(svga); svga_init_draw_functions(svga); svga_init_flush_functions(svga); svga_init_misc_functions(svga); svga_init_rasterizer_functions(svga); svga_init_sampler_functions(svga); svga_init_fs_functions(svga); svga_init_vs_functions(svga); svga_init_gs_functions(svga); svga_init_vertex_functions(svga); svga_init_constbuffer_functions(svga); svga_init_query_functions(svga); svga_init_surface_functions(svga); svga_init_stream_output_functions(svga); /* init misc state */ svga->curr.sample_mask = ~0; /* debug */ svga->debug.no_swtnl = debug_get_option_no_swtnl(); svga->debug.force_swtnl = debug_get_option_force_swtnl(); svga->debug.use_min_mipmap = debug_get_option_use_min_mipmap(); svga->debug.disable_shader = debug_get_option_disable_shader(); svga->debug.no_line_width = debug_get_option_no_line_width(); svga->debug.force_hw_line_stipple = debug_get_option_force_hw_line_stipple(); if (!(svga->blend_object_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->ds_object_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->input_element_object_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->rast_object_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->sampler_object_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->sampler_view_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->shader_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->surface_view_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->stream_output_id_bm = util_bitmask_create())) goto cleanup; if (!(svga->query_id_bm = util_bitmask_create())) goto cleanup; svga->hwtnl = svga_hwtnl_create(svga); if (svga->hwtnl == NULL) goto cleanup; if (!svga_init_swtnl(svga)) goto cleanup; ret = svga_emit_initial_state( svga ); if (ret != PIPE_OK) goto cleanup; svga->const0_upload = u_upload_create(&svga->pipe, CONST0_UPLOAD_DEFAULT_SIZE, CONST0_UPLOAD_ALIGNMENT, PIPE_BIND_CONSTANT_BUFFER); if (!svga->const0_upload) goto cleanup; /* Avoid shortcircuiting state with initial value of zero. */ memset(&svga->state.hw_clear, 0xcd, sizeof(svga->state.hw_clear)); memset(&svga->state.hw_clear.framebuffer, 0x0, sizeof(svga->state.hw_clear.framebuffer)); memset(&svga->state.hw_draw, 0xcd, sizeof(svga->state.hw_draw)); memset(&svga->state.hw_draw.views, 0x0, sizeof(svga->state.hw_draw.views)); memset(&svga->state.hw_draw.num_sampler_views, 0, sizeof(svga->state.hw_draw.num_sampler_views)); svga->state.hw_draw.num_views = 0; /* Initialize the shader pointers */ svga->state.hw_draw.vs = NULL; svga->state.hw_draw.gs = NULL; svga->state.hw_draw.fs = NULL; memset(svga->state.hw_draw.constbuf, 0, sizeof(svga->state.hw_draw.constbuf)); memset(svga->state.hw_draw.default_constbuf_size, 0, sizeof(svga->state.hw_draw.default_constbuf_size)); memset(svga->state.hw_draw.enabled_constbufs, 0, sizeof(svga->state.hw_draw.enabled_constbufs)); /* Create a no-operation blend state which we will bind whenever the * requested blend state is impossible (e.g. due to having an integer * render target attached). * * XXX: We will probably actually need 16 of these, one for each possible * RGBA color mask (4 bits). Then, we would bind the one with a color mask * matching the blend state it is replacing. */ { struct pipe_blend_state noop_tmpl = {0}; unsigned i; for (i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) { // Set the color mask to all-ones. Later this may change. noop_tmpl.rt[i].colormask = PIPE_MASK_RGBA; } svga->noop_blend = svga->pipe.create_blend_state(&svga->pipe, &noop_tmpl); } svga->dirty = ~0; return &svga->pipe; cleanup: svga_destroy_swtnl(svga); if (svga->const0_upload) u_upload_destroy(svga->const0_upload); if (svga->hwtnl) svga_hwtnl_destroy(svga->hwtnl); if (svga->swc) svga->swc->destroy(svga->swc); util_bitmask_destroy(svga->blend_object_id_bm); util_bitmask_destroy(svga->ds_object_id_bm); util_bitmask_destroy(svga->input_element_object_id_bm); util_bitmask_destroy(svga->rast_object_id_bm); util_bitmask_destroy(svga->sampler_object_id_bm); util_bitmask_destroy(svga->sampler_view_id_bm); util_bitmask_destroy(svga->shader_id_bm); util_bitmask_destroy(svga->surface_view_id_bm); util_bitmask_destroy(svga->stream_output_id_bm); util_bitmask_destroy(svga->query_id_bm); FREE(svga); return NULL; }
static struct pipe_context * ilo_context_create(struct pipe_screen *screen, void *priv) { struct ilo_screen *is = ilo_screen(screen); struct ilo_context *ilo; ilo = CALLOC_STRUCT(ilo_context); if (!ilo) return NULL; ilo->winsys = is->winsys; ilo->dev = &is->dev; /* * initialize first, otherwise it may not be safe to call * ilo_context_destroy() on errors */ util_slab_create(&ilo->transfer_mempool, sizeof(struct ilo_transfer), 64, UTIL_SLAB_SINGLETHREADED); /* 8192 DWords */ ilo->cp = ilo_cp_create(ilo->winsys, 8192, is->dev.has_llc); ilo->shader_cache = ilo_shader_cache_create(); if (ilo->cp) ilo->hw3d = ilo_3d_create(ilo->cp, ilo->dev); if (!ilo->cp || !ilo->shader_cache || !ilo->hw3d) { ilo_context_destroy(&ilo->base); return NULL; } ilo_cp_set_flush_callback(ilo->cp, ilo_context_cp_flushed, (void *) ilo); ilo->base.screen = screen; ilo->base.priv = priv; ilo->base.destroy = ilo_context_destroy; ilo->base.flush = ilo_flush; ilo_init_3d_functions(ilo); ilo_init_query_functions(ilo); ilo_init_state_functions(ilo); ilo_init_blit_functions(ilo); ilo_init_transfer_functions(ilo); ilo_init_video_functions(ilo); ilo_init_gpgpu_functions(ilo); ilo_init_states(ilo); /* * These must be called last as u_upload/u_blitter are clients of the pipe * context. */ ilo->uploader = u_upload_create(&ilo->base, 1024 * 1024, 16, PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_INDEX_BUFFER); if (!ilo->uploader) { ilo_context_destroy(&ilo->base); return NULL; } ilo->blitter = ilo_blitter_create(ilo); if (!ilo->blitter) { ilo_context_destroy(&ilo->base); return NULL; } return &ilo->base; }
struct u_upload_mgr * u_upload_clone(struct pipe_context *pipe, struct u_upload_mgr *upload) { return u_upload_create(pipe, upload->default_size, upload->bind, upload->usage, upload->flags); }
static struct st_context * st_create_context_priv( struct gl_context *ctx, struct pipe_context *pipe, const struct st_config_options *options) { struct pipe_screen *screen = pipe->screen; uint i; struct st_context *st = ST_CALLOC_STRUCT( st_context ); st->options = *options; ctx->st = st; st->ctx = ctx; st->pipe = pipe; /* XXX: this is one-off, per-screen init: */ st_debug_init(); /* state tracker needs the VBO module */ _vbo_CreateContext(ctx); st->dirty.mesa = ~0; st->dirty.st = ~0; /* Create upload manager for vertex data for glBitmap, glDrawPixels, * glClear, etc. */ st->uploader = u_upload_create(st->pipe, 65536, 4, PIPE_BIND_VERTEX_BUFFER); if (!screen->get_param(screen, PIPE_CAP_USER_INDEX_BUFFERS)) { st->indexbuf_uploader = u_upload_create(st->pipe, 128 * 1024, 4, PIPE_BIND_INDEX_BUFFER); } if (!screen->get_param(screen, PIPE_CAP_USER_CONSTANT_BUFFERS)) { unsigned alignment = screen->get_param(screen, PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT); st->constbuf_uploader = u_upload_create(pipe, 128 * 1024, alignment, PIPE_BIND_CONSTANT_BUFFER); } st->cso_context = cso_create_context(pipe); st_init_atoms( st ); st_init_bitmap(st); st_init_clear(st); st_init_draw( st ); st_init_generate_mipmap(st); /* Choose texture target for glDrawPixels, glBitmap, renderbuffers */ if (pipe->screen->get_param(pipe->screen, PIPE_CAP_NPOT_TEXTURES)) st->internal_target = PIPE_TEXTURE_2D; else st->internal_target = PIPE_TEXTURE_RECT; /* Vertex element objects used for drawing rectangles for glBitmap, * glDrawPixels, glClear, etc. */ for (i = 0; i < Elements(st->velems_util_draw); i++) { memset(&st->velems_util_draw[i], 0, sizeof(struct pipe_vertex_element)); st->velems_util_draw[i].src_offset = i * 4 * sizeof(float); st->velems_util_draw[i].instance_divisor = 0; st->velems_util_draw[i].vertex_buffer_index = cso_get_aux_vertex_buffer_slot(st->cso_context); st->velems_util_draw[i].src_format = PIPE_FORMAT_R32G32B32A32_FLOAT; } /* we want all vertex data to be placed in buffer objects */ vbo_use_buffer_objects(ctx); /* make sure that no VBOs are left mapped when we're drawing. */ vbo_always_unmap_buffers(ctx); /* Need these flags: */ st->ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; st->ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; st->pixel_xfer.cache = _mesa_new_program_cache(); st->has_stencil_export = screen->get_param(screen, PIPE_CAP_SHADER_STENCIL_EXPORT); st->has_shader_model3 = screen->get_param(screen, PIPE_CAP_SM3); st->prefer_blit_based_texture_transfer = screen->get_param(screen, PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER); st->needs_texcoord_semantic = screen->get_param(screen, PIPE_CAP_TGSI_TEXCOORD); st->apply_texture_swizzle_to_border_color = !!(screen->get_param(screen, PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK) & (PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 | PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600)); /* GL limits and extensions */ st_init_limits(st); st_init_extensions(st); _mesa_compute_version(ctx); _mesa_initialize_dispatch_tables(ctx); _mesa_initialize_vbo_vtxfmt(ctx); return st; }
.src_format = PIPE_FORMAT_R32G32B32_FLOAT, }}); fd4_ctx->solid_vbuf_state.vertexbuf.count = 1; fd4_ctx->solid_vbuf_state.vertexbuf.vb[0].stride = 12; fd4_ctx->solid_vbuf_state.vertexbuf.vb[0].buffer = fd4_ctx->solid_vbuf; /* setup blit_vbuf_state: */ fd4_ctx->blit_vbuf_state.vtx = pctx->create_vertex_elements_state( pctx, 2, (struct pipe_vertex_element[]){{ .vertex_buffer_index = 0, .src_offset = 0, .src_format = PIPE_FORMAT_R32G32_FLOAT, }, { .vertex_buffer_index = 1, .src_offset = 0, .src_format = PIPE_FORMAT_R32G32B32_FLOAT, }}); fd4_ctx->blit_vbuf_state.vertexbuf.count = 2; fd4_ctx->blit_vbuf_state.vertexbuf.vb[0].stride = 8; fd4_ctx->blit_vbuf_state.vertexbuf.vb[0].buffer = fd4_ctx->blit_texcoord_vbuf; fd4_ctx->blit_vbuf_state.vertexbuf.vb[1].stride = 12; fd4_ctx->blit_vbuf_state.vertexbuf.vb[1].buffer = fd4_ctx->solid_vbuf; fd4_query_context_init(pctx); fd4_ctx->border_color_uploader = u_upload_create(pctx, 4096, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, 0); return pctx; }
bool r600_common_context_init(struct r600_common_context *rctx, struct r600_common_screen *rscreen, unsigned context_flags) { slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers); slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers); rctx->screen = rscreen; rctx->ws = rscreen->ws; rctx->family = rscreen->family; rctx->chip_class = rscreen->chip_class; rctx->b.invalidate_resource = r600_invalidate_resource; rctx->b.resource_commit = r600_resource_commit; rctx->b.transfer_map = u_transfer_map_vtbl; rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl; rctx->b.transfer_unmap = u_transfer_unmap_vtbl; rctx->b.texture_subdata = u_default_texture_subdata; rctx->b.memory_barrier = r600_memory_barrier; rctx->b.flush = r600_flush_from_st; rctx->b.set_debug_callback = r600_set_debug_callback; rctx->b.fence_server_sync = r600_fence_server_sync; rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback; /* evergreen_compute.c has a special codepath for global buffers. * Everything else can use the direct path. */ if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) && (context_flags & PIPE_CONTEXT_COMPUTE_ONLY)) rctx->b.buffer_subdata = u_default_buffer_subdata; else rctx->b.buffer_subdata = r600_buffer_subdata; if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) { rctx->b.get_device_reset_status = r600_get_reset_status; rctx->gpu_reset_counter = rctx->ws->query_value(rctx->ws, RADEON_GPU_RESET_COUNTER); } rctx->b.set_device_reset_callback = r600_set_device_reset_callback; r600_init_context_texture_functions(rctx); r600_init_viewport_functions(rctx); r600_streamout_init(rctx); r600_query_init(rctx); cayman_init_msaa(&rctx->b); rctx->allocator_zeroed_memory = u_suballocator_create(&rctx->b, rscreen->info.gart_page_size, 0, PIPE_USAGE_DEFAULT, 0, true); if (!rctx->allocator_zeroed_memory) return false; rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024, 0, PIPE_USAGE_STREAM); if (!rctx->b.stream_uploader) return false; rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024, 0, PIPE_USAGE_DEFAULT); if (!rctx->b.const_uploader) return false; rctx->ctx = rctx->ws->ctx_create(rctx->ws); if (!rctx->ctx) return false; if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) { rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA, r600_flush_dma_ring, rctx); rctx->dma.flush = r600_flush_dma_ring; } return true; }
static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) { struct r600_context *rctx = CALLOC_STRUCT(r600_context); struct r600_screen* rscreen = (struct r600_screen *)screen; int shader, i; if (rctx == NULL) return NULL; if (!r600_common_context_init(&rctx->b, &rscreen->b)) goto fail; rctx->b.b.screen = screen; rctx->b.b.priv = priv; rctx->b.b.destroy = r600_destroy_context; rctx->b.b.flush = r600_flush_from_st; /* Easy accessing of screen/winsys. */ rctx->screen = rscreen; si_init_blit_functions(rctx); r600_init_query_functions(rctx); r600_init_context_resource_functions(rctx); si_init_compute_functions(rctx); if (rscreen->b.info.has_uvd) { rctx->b.b.create_video_codec = radeonsi_uvd_create_decoder; rctx->b.b.create_video_buffer = radeonsi_video_buffer_create; } else { rctx->b.b.create_video_codec = vl_create_decoder; rctx->b.b.create_video_buffer = vl_video_buffer_create; } rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL); rctx->b.rings.gfx.flush = r600_flush_from_winsys; si_init_all_descriptors(rctx); /* Initialize cache_flush. */ rctx->cache_flush = si_atom_cache_flush; rctx->atoms.cache_flush = &rctx->cache_flush; rctx->atoms.streamout_begin = &rctx->b.streamout.begin_atom; switch (rctx->b.chip_class) { case SI: case CIK: si_init_state_functions(rctx); LIST_INITHEAD(&rctx->active_nontimer_query_list); rctx->max_db = 8; si_init_config(rctx); break; default: R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class); goto fail; } rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx); util_slab_create(&rctx->pool_transfers, sizeof(struct pipe_transfer), 64, UTIL_SLAB_SINGLETHREADED); rctx->uploader = u_upload_create(&rctx->b.b, 1024 * 1024, 256, PIPE_BIND_INDEX_BUFFER | PIPE_BIND_CONSTANT_BUFFER); if (!rctx->uploader) goto fail; rctx->blitter = util_blitter_create(&rctx->b.b); if (rctx->blitter == NULL) goto fail; rctx->dummy_pixel_shader = util_make_fragment_cloneinput_shader(&rctx->b.b, 0, TGSI_SEMANTIC_GENERIC, TGSI_INTERPOLATE_CONSTANT); rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader); /* these must be last */ si_begin_new_cs(rctx); si_get_backend_mask(rctx); /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy * with a NULL buffer). We need to use a dummy buffer instead. */ if (rctx->b.chip_class == CIK) { rctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STATIC, 16); rctx->null_const_buf.buffer_size = rctx->null_const_buf.buffer->width0; for (shader = 0; shader < SI_NUM_SHADERS; shader++) { for (i = 0; i < NUM_CONST_BUFFERS; i++) { rctx->b.b.set_constant_buffer(&rctx->b.b, shader, i, &rctx->null_const_buf); } } /* Clear the NULL constant buffer, because loads should return zeros. */ rctx->b.clear_buffer(&rctx->b.b, rctx->null_const_buf.buffer, 0, rctx->null_const_buf.buffer->width0, 0); } return &rctx->b.b; fail: r600_destroy_context(&rctx->b.b); return NULL; }