static void dump_INTC_regs(void)
{
unsigned int pendingIrqs,pendingIrqs1, pendingIrqs2, mask0, mask1, mask2;
char msg[80];
pendingIrqs = CPUINT1C->IntrW0Status;
pendingIrqs &= ~(mask0 = CPUINT1C->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C->IntrW1Status;
pendingIrqs1 &= ~(mask1 = CPUINT1C->IntrW1MaskStatus);
pendingIrqs2 = CPUINT1C->IntrW2Status;
pendingIrqs2 &= ~(mask2 = CPUINT1C->IntrW2MaskStatus);
sprintf(msg, "\nLast pending0=%08x, pd1=%08x, pd2=%08x\n",
gDebugPendingIrq0, gDebugPendingIrq1, gDebugPendingIrq2);
uartB_puts(msg);
sprintf(msg, "Last MaskW0=%08x, mW1=%08x, mW2=%08x\n",
gDebugMaskW0, gDebugMaskW1, gDebugMaskW2);
uartB_puts(msg);
sprintf(msg, "Current pending0=%08x, pd1=%08x, pd2=%08x\n",
pendingIrqs, pendingIrqs1, pendingIrqs2);
uartB_puts(msg);
sprintf(msg, "Current MaskW0=%08x, mW1=%08x, mW2=%08x\n",
mask0, mask1, mask2);
uartB_puts(msg);
}
unsigned long serial_init(int chan, void *ignored)
{
unsigned long uartBaseAddr = UARTA_ADR_BASE + (0x40 * chan);
void uartB_puts(const char *s);
#define DIVISOR (44)
shift = 2;
/* UARTA has already been initialized by the bootloader */
if (chan > 0) {
//turn_on_mux(chan);
// Write DLAB, and (8N1) = 0x83
writel(UART_LCR_DLAB|UART_LCR_WLEN8, (void *)(uartBaseAddr + (UART_LCR << shift)));
// Write DLL to 0xe
writel(DIVISOR, (void *)(uartBaseAddr + (UART_DLL << shift)));
writel(0, (void *)(uartBaseAddr + (UART_DLM << shift)));
// Clear DLAB
writel(UART_LCR_WLEN8, (void *)(uartBaseAddr + (UART_LCR << shift)));
// Disable FIFO
writel(0, (void *)(uartBaseAddr + (UART_FCR << shift)));
if (chan == 1) {
uartB_puts("Done initializing UARTB\n");
}
}
return (uartBaseAddr);
}
void brcm_mips_int7_dispatch(struct pt_regs *regs)
{
static int intNo = 0;
#if !defined(DEBUG_UARTA)
/* debug debug add ADT */
if ((intNo++) == 0) {
printk("brcm timer int\n");
if (intNo >= HEARTBEAT_FREQ) /* Wrap */
intNo = 1;
}
#elif defined(DEBUG_UARTA_INTR_FROM_TIMERIRQ)
// Print heart beat
if ((intNo++) % HEARTBEAT_FREQ == 0)
{
char msg[40];
sprintf(msg, "----> hb jif=%lu:\n", jiffies);
uartB_puts(msg);
dump_INTC_regs();
}
#endif // !defined(DEBUG_UARTA)
#if defined(CONFIG_SMP) && ! defined(CONFIG_MIPS_MT)
{
int cpu = smp_processor_id();
do_IRQ(cpu ? BCM_LINUX_SYSTIMER_1_IRQ : BCM_LINUX_SYSTIMER_IRQ, regs);
}
#else
do_IRQ(BCM_LINUX_SYSTIMER_IRQ, regs);
#endif
}
void
uartB_init(void)
{
// MUX for UARTB :
// bits 5:3 Value 0x2 for Tx
// bits 8:6 Value 0x2 for Rx
// Do this until CFE initializes it correctly
#define SUN_TOP_CTRL_PIN_MUX_CTRL_6 (0xb0404118)
volatile unsigned long* pSunTopMuxCtrl6 = (volatile unsigned long*) SUN_TOP_CTRL_PIN_MUX_CTRL_6;
*pSunTopMuxCtrl6 &= 0xFFFFFE07; // Clear the bits
*pSunTopMuxCtrl6 |= 0x00000090; // set (5:3) to 2, (8:6) to 2
uartB_puts("UARTB initialization is completed! \r\n");
}
unsigned long serial_init(int chan, void *ignored)
{
#if defined (CONFIG_BOOT_RAW) || !defined (CONFIG_HAS_ADV_CFE)
unsigned long uartBaseAddr = UARTA_ADR_BASE + (0x40 * chan);
#else
unsigned long uartBaseAddr = cfe_uarts[chan].base_address;
#endif
void uartB_puts(const char *s);
#define DIVISOR cfe_uarts[chan].divisor
shift = 2;
#ifndef CONFIG_BOOT_RAW
/* ttyS0 has already been initialized by the bootloader */
if (chan > 0 )
#endif
{
// Write DLAB, and (8N1) = 0x83
writel(UART_LCR_DLAB|UART_LCR_WLEN8, (void *)(uartBaseAddr + (UART_LCR << shift)));
// Write DLL to 0xe
writel(DIVISOR, (void *)(uartBaseAddr + (UART_DLL << shift)));
writel(0, (void *)(uartBaseAddr + (UART_DLM << shift)));
// Clear DLAB
writel(UART_LCR_WLEN8, (void *)(uartBaseAddr + (UART_LCR << shift)));
// Disable FIFO
writel(0, (void *)(uartBaseAddr + (UART_FCR << shift)));
if (chan == 1) {
uartB_puts("Done initializing UARTB\n");
}
}
return (uartBaseAddr);
}
unsigned long serial_init(int chan, void *ignored)
{
#if 0
struct serial_struct req;
/* UARTA has already been initialized by the bootloader */
if (chan > 0) {
memset(&req, 0, sizeof(struct serial_struct));
req.port = chan;
req.iomem_base = UARTA_ADR_BASE + (0x40 * chan);
req.irq = BRCM_SERIAL1_IRQ + chan; // FOr now, assume all 3 irqs are consecutive
req.baud_base = BRCM_BASE_BAUD;
req.xmit_fifo_size = 32;
/* How far apart the registers are. */
req.iomem_reg_shift = shift = 2; /* Offset by 4 bytes, UART_SDW_LCR=0c offset, UART_LCR=3 */
req.io_type = SERIAL_IO_MEM;
req.flags = STD_COM_FLAGS;
req.iomap_base = chan;
register_serial(&req);
}
#endif
unsigned long uartBaseAddr = UARTA_ADR_BASE + (0x40 * chan);
void uartB_puts(const char *s);
#ifdef CONFIG_MIPS_BRCM_IKOS
#define DIVISOR (14)
#else
#define DIVISOR (44)
#endif
shift = 2;
#if 1 /* Enable UARTB */
if (chan == 1) {
// MUX for UARTB is: RX: ctrl3: bit 29:27 (001'b) and TX: ctrl4: bit 02:00 (001'b)
#define SUN_TOP_CTRL_PIN_MUX_CTRL_3 (0xb040410c)
volatile unsigned long* pSunTopMuxCtrl3 = (volatile unsigned long*) SUN_TOP_CTRL_PIN_MUX_CTRL_3;
#define SUN_TOP_CTRL_PIN_MUX_CTRL_4 (0xb0404110)
volatile unsigned long* pSunTopMuxCtrl4 = (volatile unsigned long*) SUN_TOP_CTRL_PIN_MUX_CTRL_4;
*pSunTopMuxCtrl3 &= 0xc7ffffff; // Clear it
*pSunTopMuxCtrl3 |= 0x08000000; // Write 001'b at 27:29
*pSunTopMuxCtrl4 &= 0xfffffff8; // Clear it
*pSunTopMuxCtrl4 |= 0x00000001; // Write 001'b at 00:02
}
#endif
/* UARTA has already been initialized by the bootloader */
if (chan > 0 ) {
// Write DLAB, and (8N1) = 0x83
writel(UART_LCR_DLAB|UART_LCR_WLEN8, (void *)(uartBaseAddr + (UART_LCR << shift)));
// Write DLL to 0xe
writel(DIVISOR, (void *)(uartBaseAddr + (UART_DLL << shift)));
writel(0, (void *)(uartBaseAddr + (UART_DLM << shift)));
// Clear DLAB
writel(UART_LCR_WLEN8, (void *)(uartBaseAddr + (UART_LCR << shift)));
// Disable FIFO
writel(0, (void *)(uartBaseAddr + (UART_FCR << shift)));
if (chan == 1) {
uartB_puts("Done initializing UARTB\n");
}
}
return (uartBaseAddr);
}