Esempio n. 1
0
void uartInit(uint32_t baudrate)
{
  uint32_t fDiv;
  uint32_t regVal=regVal;

  #if defined CFG_MCU_FAMILY_LPC11UXX
    NVIC_DisableIRQ(UART_IRQn);
  #elif defined CFG_MCU_FAMILY_LPC13UXX
    NVIC_DisableIRQ(USART_IRQn);
  #endif

  /* Clear protocol control blocks */
  memset(&uart_pcb, 0, sizeof(uart_pcb_t));
  uart_pcb.pending_tx_data = 0;
  uartRxBufferInit();

  /* Set 1.14 UART RXD */
  //this shouldn't be here...
  //LPC_IOCON->PIO1_14 &= ~0x0F;
  //LPC_IOCON->PIO1_14 |= 0x03;

  /* Set 1.13 UART TXD */
  //LPC_IOCON->PIO1_13 &= ~0x0F;
  //LPC_IOCON->PIO1_13 |= 0x03;

#if defined UART_RTS_CTS_FLOWCONTROL
  /* start RTS/CTS flow control setup - davidson 130531 */
  //LPC_IOCON->PIO0_7 &= ~0x07;   /* Flow control CTS UART I/O Config  Type Input */
  //LPC_IOCON->PIO0_7 |= 0x01; 

  //LPC_IOCON->PIO1_17 &= ~0x07;  /* Flow control RTS UART I/O Config  Type Output */
  //LPC_IOCON->PIO1_17 |= 0x01;  
  /* end of RTS/CTS flow control setup */
#endif  
  
  /* Enable UART clock */
  LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
  LPC_SYSCON->UARTCLKDIV = 1;

  /* 8 bits, no Parity, 1 Stop bit */
  LPC_USART->LCR = (USART_LCR_Word_Length_Select_8Chars |
                USART_LCR_Stop_Bit_Select_1Bits |
                USART_LCR_Parity_Disabled |
                USART_LCR_Parity_Select_OddParity |
                USART_LCR_Break_Control_Disabled |
                USART_LCR_Divisor_Latch_Access_Enabled);

  /* Baud rate */
  regVal = LPC_SYSCON->UARTCLKDIV;
  fDiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate;

  LPC_USART->DLM = fDiv / 256;
  LPC_USART->DLL = fDiv % 256;

  /* Set DLAB back to 0 */
  LPC_USART->LCR = (USART_LCR_Word_Length_Select_8Chars |
                USART_LCR_Stop_Bit_Select_1Bits |
                USART_LCR_Parity_Disabled |
                USART_LCR_Parity_Select_OddParity |
                USART_LCR_Break_Control_Disabled |
                USART_LCR_Divisor_Latch_Access_Disabled);

  /* Enable and reset TX and RX FIFO. */
  LPC_USART->FCR = (USART_FCR_FIFO_Enabled |
                USART_FCR_Rx_FIFO_Reset |
                USART_FCR_Tx_FIFO_Reset);

#if defined UART_RTS_CTS_FLOWCONTROL
  /* Enable Auto RTS and Auto CTS  - davidson 130531 */
  LPC_UART->MCR = 0xC0;
#endif
                
  /* Read to clear the line status. */
  regVal = LPC_USART->LSR;

  /* Ensure a clean start, no data in either TX or RX FIFO. */
  while (( LPC_USART->LSR & (USART_LSR_THRE|USART_LSR_TEMT)) != (USART_LSR_THRE|USART_LSR_TEMT) );
  while ( LPC_USART->LSR & USART_LSR_RDR_DATA )
  {
    /* Dump data from RX FIFO */
    regVal = LPC_USART->RBR;
  }

  /* Set the initialised flag in the protocol control block */
  uart_pcb.initialised = 1;
  uart_pcb.baudrate = baudrate;

  /* Enable the UART Interrupt */
  #if defined CFG_MCU_FAMILY_LPC11UXX
    NVIC_EnableIRQ(UART_IRQn);
  #elif defined CFG_MCU_FAMILY_LPC13UXX
    NVIC_EnableIRQ(USART_IRQn);
  #endif
  LPC_USART->IER = USART_IER_RBR_Interrupt_Enabled | USART_IER_RLS_Interrupt_Enabled;

  return;
}
Esempio n. 2
0
void uartInit(uint32_t baudrate)
{
  uint32_t fDiv;
  uint32_t regVal;

  NVIC_DisableIRQ(UART_IRQn);

  // Clear protocol control blocks
  memset(&pcb, 0, sizeof(uart_pcb_t));
  pcb.pending_tx_data = 0;
  uartRxBufferInit();

  /* Set 1.6 UART RXD */
  IOCON_PIO1_6 &= ~IOCON_PIO1_6_FUNC_MASK;
  IOCON_PIO1_6 |= IOCON_PIO1_6_FUNC_UART_RXD;

  /* Set 1.7 UART TXD */
  IOCON_PIO1_7 &= ~IOCON_PIO1_7_FUNC_MASK;	
  IOCON_PIO1_7 |= IOCON_PIO1_7_FUNC_UART_TXD;

  /* Enable UART clock */
  SCB_SYSAHBCLKCTRL |= (SCB_SYSAHBCLKCTRL_UART);
  SCB_UARTCLKDIV = SCB_UARTCLKDIV_DIV1;     /* divided by 1 */

  /* 8 bits, no Parity, 1 Stop bit */
  UART_U0LCR = (UART_U0LCR_Word_Length_Select_8Chars |
                UART_U0LCR_Stop_Bit_Select_1Bits |
                UART_U0LCR_Parity_Disabled |
                UART_U0LCR_Parity_Select_OddParity |
                UART_U0LCR_Break_Control_Disabled |
                UART_U0LCR_Divisor_Latch_Access_Enabled);

  /* Baud rate */
  regVal = SCB_UARTCLKDIV;
  fDiv = (((CFG_CPU_CCLK * SCB_SYSAHBCLKDIV)/regVal)/16)/baudrate;

  UART_U0DLM = fDiv / 256;
  UART_U0DLL = fDiv % 256;
  
  /* Set DLAB back to 0 */
  UART_U0LCR = (UART_U0LCR_Word_Length_Select_8Chars |
                UART_U0LCR_Stop_Bit_Select_1Bits |
                UART_U0LCR_Parity_Disabled |
                UART_U0LCR_Parity_Select_OddParity |
                UART_U0LCR_Break_Control_Disabled |
                UART_U0LCR_Divisor_Latch_Access_Disabled);
  
  /* Enable and reset TX and RX FIFO. */
  UART_U0FCR = (UART_U0FCR_FIFO_Enabled | 
                UART_U0FCR_Rx_FIFO_Reset | 
                UART_U0FCR_Tx_FIFO_Reset); 

  /* Read to clear the line status. */
  regVal = UART_U0LSR;

  /* Ensure a clean start, no data in either TX or RX FIFO. */
  while (( UART_U0LSR & (UART_U0LSR_THRE|UART_U0LSR_TEMT)) != (UART_U0LSR_THRE|UART_U0LSR_TEMT) );
  while ( UART_U0LSR & UART_U0LSR_RDR_DATA )
  {
    /* Dump data from RX FIFO */
    regVal = UART_U0RBR;
  }

  /* Set the initialised flag in the protocol control block */
  pcb.initialised = 1;

  /* Enable the UART Interrupt */
  NVIC_EnableIRQ(UART_IRQn);
  UART_U0IER = UART_U0IER_RBR_Interrupt_Enabled | UART_U0IER_RLS_Interrupt_Enabled;

  return;
}