void uart_sps_init(uint8_t baudr, uint8_t mode ) { //ENABLE FIFO, REGISTER FCR IF UART_LCR_REG.DLAB=0 SetBits16(UART_LCR_REG, UART_DLAB, 0); // XMIT FIFO RESET, RCVR FIFO RESET, FIFO ENABLED, SetWord16(UART_IIR_FCR_REG,0x87); //rcv int when rx fifo 1/2 full //SetWord16(UART_IIR_FCR_REG,0xC7); //rcv int when rx fifo 14/16 full /* this option will cause the sps application to overflow the Rx FIFO */ //DISABLE INTERRUPTS, REGISTER IER IF UART_LCR_REG.DLAB=0 SetWord16(UART_IER_DLH_REG, 0); // ACCESS DIVISORLATCH REGISTER FOR BAUDRATE, REGISTER UART_DLH/DLL_REG IF UART_LCR_REG.DLAB=1 SetBits16(UART_LCR_REG, UART_DLAB, 1); SetWord16(UART_IER_DLH_REG,0); SetWord16(UART_IER_DLH_REG, (baudr&0xFF>>0x8)); SetWord16(UART_RBR_THR_DLL_REG,baudr&0xFF); // NO PARITY, 1 STOP BIT, 8 DATA LENGTH SetWord16(UART_LCR_REG, mode); //ENABLE TX INTERRUPTS, REGISTER IER IF UART_LCR_REG.DLAB=0 SetBits16(UART_LCR_REG, UART_DLAB, 0); NVIC_DisableIRQ(UART_IRQn); NVIC_SetPriority(UART_IRQn,1); NVIC_EnableIRQ(UART_IRQn); NVIC_ClearPendingIRQ(UART_IRQn); // Configure UART environment uart_sps_env.errordetect = UART_ERROR_DETECT_DISABLED; uart_sps_env.rx.bufptr = NULL; uart_sps_env.rx.state = NULL; uart_sps_env.rx.size = 0; uart_sps_env.tx.bufptr = NULL; uart_sps_env.tx.state = NULL; uart_sps_env.tx.size = 0; uart_sps_flow_off(); }
void uart_sps_init(uint8_t baudr, uint8_t mode ) { //ENABLE FIFO, REGISTER FCR IF UART_LCR_REG.DLAB=0 SetBits16(UART_LCR_REG, UART_DLAB, 0); // XMIT FIFO RESET, RCVR FIFO RESET, FIFO ENABLED, SetWord16(UART_IIR_FCR_REG,0x87); //rcv int when rx fifo 1/2 full //SetWord16(UART_IIR_FCR_REG,0xC7); //rcv int when rx fifo 14/16 full /* this option will cause the sps application to overflow the Rx FIFO */ //DISABLE INTERRUPTS, REGISTER IER IF UART_LCR_REG.DLAB=0 SetWord16(UART_IER_DLH_REG, 0); // ACCESS DIVISORLATCH REGISTER FOR BAUDRATE, REGISTER UART_DLH/DLL_REG IF UART_LCR_REG.DLAB=1 SetBits16(UART_LCR_REG, UART_DLAB, 1); SetWord16(UART_IER_DLH_REG,0); SetWord16(UART_IER_DLH_REG, (baudr&0xFF>>0x8)); SetWord16(UART_RBR_THR_DLL_REG,baudr&0xFF); // NO PARITY, 1 STOP BIT, 8 DATA LENGTH SetWord16(UART_LCR_REG, mode); //ENABLE TX INTERRUPTS, REGISTER IER IF UART_LCR_REG.DLAB=0 SetBits16(UART_LCR_REG, UART_DLAB, 0); NVIC_EnableIRQ(UART_IRQn); NVIC->ICPR[UART_IRQn]=1; //clear eventual pending bit, but not necessary becasuse this is already cleared automatically in HW // Configure UART environment uart_sps_env.errordetect = UART_ERROR_DETECT_DISABLED; uart_sps_env.rx.bufptr = NULL; uart_sps_env.rx.state = NULL; uart_sps_env.rx.size = 0; uart_sps_env.tx.bufptr = NULL; uart_sps_env.tx.state = NULL; uart_sps_env.tx.size = 0; uart_sps_flow_off(); //turn rts/cts flow control off //SetWord32(UART_MCR_REG, UART_AFCE|UART_RTS); //Enable RTS/CTS handshake /*is not tested in sps application*/ //uart_write("uart_is_initialised",19); }