static void usart_handler(uint8_t port) { Usart* usart = get_usart(port); uint32_t sr = usart_get_status(usart); if (sr & US_CSR_RXRDY) { // Data received ui_com_tx_start(); uint32_t value; bool b_error = usart_read(usart, &value) || (sr & (US_CSR_FRAME | US_CSR_TIMEOUT | US_CSR_PARE)); if (b_error) { usart_reset_rx(usart); usart_enable_rx(usart); udi_cdc_multi_signal_framing_error(port); ui_com_error(); } // Transfer UART RX fifo to CDC TX if (!udi_cdc_multi_is_tx_ready(port)) { // Fifo full udi_cdc_multi_signal_overrun(port); ui_com_overflow(); } else { udi_cdc_multi_putc(port, value); } ui_com_tx_stop(); return; } if (sr & US_CSR_TXRDY) { // Data send if (udi_cdc_multi_is_rx_ready(port)) { // Transmit next data ui_com_rx_start(); int c = udi_cdc_multi_getc(port); usart_write(usart, c); } else { // Fifo empty then Stop UART transmission usart_disable_tx(usart); usart_disable_interrupt(usart, US_IDR_TXRDY); ui_com_rx_stop(); } } }
/** * \internal * \brief USART interrupt callback function * * Called by USART driver when receiving is complete. * * * \param module USART module causing the interrupt (not used) */ static void usart_rx_callback(struct usart_module *const module) { /* Data received */ ui_com_tx_start(); /* Transfer UART RX fifo to CDC TX */ if (!udi_cdc_is_tx_ready()) { /* Fifo full */ udi_cdc_signal_overrun(); ui_com_overflow(); } else { udi_cdc_putc(rx_data); } ui_com_tx_stop(); usart_read_buffer_job(&usart_module_edbg, &rx_data, 1); return; }