Esempi in C++ (Cpp) per unisims_ver_m_00000000001946988858_2297623829_init

Esempio n. 1

File: testbench_lb_isim_beh.exe_main.c Progetto: carchard/ECE5760_Epiphyte

int main(int argc, char **argv)
{
    xsi_init_design(argc, argv);
    xsi_register_info(&xsi_info);

    xsi_register_min_prec_unit(-12);
    unisims_ver_m_00000000001946988858_2297623829_init();
    unisims_ver_m_00000000004091665089_1189909065_init();
    unisims_ver_m_00000000003084551676_4128872403_init();
    unisims_ver_m_00000000003266096158_2593380106_init();
    work_m_00000000001861837677_1799344816_init();
    unisims_ver_m_00000000002304772977_3342287592_init();
    work_m_00000000000109744433_0948142031_init();
    work_m_00000000003859242240_0734669027_init();
    work_m_00000000003016420439_0633363268_init();
    work_m_00000000003794424252_0261495644_init();
    work_m_00000000002723099600_3271590914_init();
    work_m_00000000003413782571_2963980531_init();
    work_m_00000000000668189177_2754814804_init();
    work_m_00000000001231739293_3881718975_init();
    work_m_00000000004134447467_2073120511_init();


    xsi_register_tops("work_m_00000000001231739293_3881718975");
    xsi_register_tops("work_m_00000000004134447467_2073120511");


    return xsi_run_simulation(argc, argv);

}

Esempio n. 2

File: top_tb_isim_beh.exe_main.c Progetto: JianmingS/MIPS-architecture-CPU-design-based-on-FPGA

int main(int argc, char **argv)
{
    xsi_init_design(argc, argv);
    xsi_register_info(&xsi_info);

    xsi_register_min_prec_unit(-12);
    unisims_ver_m_00000000001946988858_2297623829_init();
    unisims_ver_m_00000000002399568039_2282143210_init();
    unisims_ver_m_00000000000740258969_3897995058_init();
    unisims_ver_m_00000000000740258969_1625843133_init();
    unisims_ver_m_00000000003131622635_0225263307_init();
    unisims_ver_m_00000000002922998384_0762524165_init();
    unisims_ver_m_00000000003266096158_2593380106_init();
    work_m_00000000000139310833_1306970619_init();
    work_m_00000000002629890179_2032185554_init();
    work_m_00000000001886194798_2244092194_init();
    work_m_00000000001638485174_0886308060_init();
    work_m_00000000003577048177_1151974483_init();
    work_m_00000000003162073797_3913188552_init();
    work_m_00000000003524194649_0967167703_init();
    work_m_00000000003380540956_3823007873_init();
    work_m_00000000000063944133_3115858369_init();
    work_m_00000000004134447467_2073120511_init();


    xsi_register_tops("work_m_00000000000063944133_3115858369");
    xsi_register_tops("work_m_00000000004134447467_2073120511");


    return xsi_run_simulation(argc, argv);

}

Esempio n. 3

File: TopModule_isim_beh.exe_main.c Progetto: tahaeghtesad/FPGA

int main(int argc, char **argv)
{
    xsi_init_design(argc, argv);
    xsi_register_info(&xsi_info);

    xsi_register_min_prec_unit(-12);
    unisims_ver_m_00000000001946988858_2297623829_init();
    unisims_ver_m_00000000004091665089_2254079252_init();
    unisims_ver_m_00000000003084551676_3140481962_init();
    unisims_ver_m_00000000003266096158_2593380106_init();
    work_m_00000000002844507051_1990981045_init();
    work_m_00000000003102653210_1967751169_init();
    work_m_00000000000620256960_2785436636_init();
    work_m_00000000002501598718_1288797228_init();
    work_m_00000000000067862790_3638803626_init();
    work_m_00000000004151216920_3217932751_init();
    work_m_00000000003065592373_0135961885_init();
    work_m_00000000004002244058_3281058526_init();
    work_m_00000000001092720650_2268903677_init();
    work_m_00000000003177940658_3706996384_init();
    work_m_00000000004134447467_2073120511_init();


    xsi_register_tops("work_m_00000000003177940658_3706996384");
    xsi_register_tops("work_m_00000000004134447467_2073120511");


    return xsi_run_simulation(argc, argv);

}