static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, void *arg)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
int irq;
#ifdef USE_ADVENCED_TIM
int irq_of;
#endif
DEBUGASSERT(dev != NULL);
irq = priv->irq;
#ifdef USE_ADVENCED_TIM
irq_of = priv->irq_of;
#endif
/* Disable interrupt when callback is removed */
if (!handler)
{
up_disable_irq(irq);
irq_detach(irq);
#ifdef USE_ADVENCED_TIM
if (priv->irq_of)
{
up_disable_irq(irq_of);
irq_detach(irq_of);
}
#endif
return OK;
}
/* Otherwise set callback and enable interrupt */
irq_attach(irq, handler, arg);
up_enable_irq(irq);
#ifdef USE_ADVENCED_TIM
if (priv->irq_of)
{
irq_attach(priv->irq_of, handler, arg);
up_enable_irq(priv->irq_of);
}
#endif
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT);
# ifdef USE_ADVENCED_TIM
if (priv->irq_of)
{
up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT);
}
# endif
#endif
return OK;
}
void up_attach_vector(int irq, int vector, vic_vector_t handler)
{
/* Verify that the IRQ number and vector number are within range */
if (irq < NR_IRQS && vector < 32 && handler)
{
int offset = vector << 2;
/* Disable all interrupts */
irqstate_t flags = irqsave();
/* Save the vector address */
vic_putreg((uint32_t)handler, VIC_VECTADDR0_OFFSET + offset);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(irq, PRIORITY_HIGHEST);
#endif
/* Enable the vectored interrupt */
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
irqrestore(flags);
}
}
void up_timerinit(void)
{
/* Configure and enable TIMER1. Used the computed TCKPS divider and timer
* match valude. The source will be either the internal PBCLOCK (TCS=0) or
* the external SOSC (TCS=1)
*/
putreg32((TIMER1_CON_TCKPS|TIMER1_CON_TCS), PIC32MX_TIMER1_CON);
putreg32(0, PIC32MX_TIMER1_CNT);
putreg32(TIMER1_MATCH-1, PIC32MX_TIMER1_PR);
putreg32(TIMER_CON_ON, PIC32MX_TIMER1_CONSET);
/* Configure the timer interrupt */
up_clrpend_irq(PIC32MX_IRQSRC_T1);
(void)up_prioritize_irq(PIC32MX_IRQ_T1, CONFIG_PIC32MX_T1PRIO);
/* Attach the timer interrupt vector */
(void)irq_attach(PIC32MX_IRQ_T1, (xcpt_t)up_timerisr);
/* And enable the timer interrupt */
up_enable_irq(PIC32MX_IRQSRC_T1);
}
void up_timerinit(void)
{
uint16_t mcr;
/* Power up Timer0 */
SCB_PCONP |= PCTIM0;
/* Timer0 clock input frequency = CCLK / TO_PCLKDIV */
SCB_PCLKSEL0 = (SCB_PCLKSEL0 & ~T0_PCLKSEL_MASK) | TIMER0_PCLKSEL;
/* Clear all match and capture event interrupts */
tmr_putreg8(TMR_IR_ALLI, TMR_IR_OFFSET);
/* Clear the timer counter */
tmr_putreg32(0, TMR_TC_OFFSET);
/* No pre-scaler */
tmr_putreg32(0, TMR_PR_OFFSET);
tmr_putreg32(0, TMR_PC_OFFSET);
/* Set timer match register to get a TICK_PER_SEC rate See arch/board.h and
* sched/os_internal.h
*/
tmr_putreg32(T0_TICKS_COUNT, TMR_MR0_OFFSET); /* 10ms Intterrupt */
/* Reset timer counter register and interrupt on match */
mcr = tmr_getreg16(TMR_MCR_OFFSET);
mcr &= ~TMR_MCR_MR1I;
mcr |= (TMR_MCR_MR0I | TMR_MCR_MR0R);
tmr_putreg16(mcr, TMR_MCR_OFFSET); /* -- bit 0=1 -int on MR0, bit 1=1 - Reset on MR0 */
/* Enable counting */
/* ~ tmr_putreg32(1, TMR_TCR_OFFSET); */
tmr_putreg8(TMR_CR_ENABLE, TMR_TCR_OFFSET);
/* Attach the timer interrupt vector */
#ifdef CONFIG_VECTORED_INTERRUPTS
up_attach_vector(IRQ_SYSTIMER, PRIORITY_HIGHEST, (vic_vector_t) up_timerisr);
#else
(void)irq_attach(IRQ_SYSTIMER, (xcpt_t) up_timerisr);
up_prioritize_irq(IRQ_SYSTIMER, PRIORITY_HIGHEST);
#endif
/* And enable the system timer interrupt */
up_enable_irq(IRQ_SYSTIMER);
}
void up_timer_initialize(void)
{
irqstate_t flags;
/* Make sure that timer0 is disabled */
flags = irqsave();
putreg16(0x0000, STR71X_TIMER0_CR1);
putreg16(0x0000, STR71X_TIMER0_CR2);
putreg16(0x0000, STR71X_TIMER0_SR);
/* Configure TIM0 so that it is clocked by the internal APB2 frequency (PCLK2)
* divided by the above prescaler value (1) -- versus an external Clock.
* -- Nothing to do because STR71X_TIMERCR1_ECKEN is already cleared.
*
* Select a divisor to reduce the frequency of clocking. This must be
* done so that the entire timer interval can fit in the 16-bit OCAR register.
* (see the discussion above).
*/
putreg16(STR71X_TIMERCR2_OCAIE | (PCLK2_DIVIDER - 1), STR71X_TIMER0_CR2);
/* Start The TIM0 Counter and enable the output comparison A */
putreg16(STR71X_TIMERCR1_EN | STR71X_TIMERCR1_OCAE, STR71X_TIMER0_CR1);
/* Setup output compare A for desired interrupt frequency. Note that
* the OCAE and OCBE bits are cleared and the pins are available for other
* functions.
*/
putreg16(OCAR_VALUE, STR71X_TIMER0_OCAR);
putreg16(0xfffc, STR71X_TIMER0_CNTR);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the timer interrupt priority */
up_prioritize_irq(STR71X_IRQ_SYSTIMER, CONFIG_TIM_PRI);
#endif
/* Attach the timer interrupt vector */
(void)irq_attach(STR71X_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
/* And enable the timer interrupt */
up_enable_irq(STR71X_IRQ_SYSTIMER);
irqrestore(flags);
}
void up_timerinit(void)
{
uint8_t reg8;
/* Clear timer counter 0 */
putreg16(0, SH1_ITU0_TCNT);
/* Set the GRA0 match value. The interrupt will be generated when TNCT
* increments to this value
*/
putreg16(TCNT_PER_TICK, SH1_ITU0_GRA);
/* Set the timer control register. TCNT cleared by FRA */
putreg8(SH1_ITUTCR_CGRA|SH1_ITUTCR_DIV, SH1_ITU0_TCR);
/* Set the timer I/O control register */
putreg8(0, SH1_ITU0_TIOR); /* GRA used but with no inputs/output pins */
/* Make sure that all status flags are clear */
putreg8(0, SH1_ITU0_TSR);
/* Attach the IMIA0 IRQ */
irq_attach(SH1_SYSTIMER_IRQ, (xcpt_t)up_timerisr);
/* Enable interrupts on GRA compare match */
putreg8(SH1_ITUTIER_IMIEA, SH1_ITU0_TIER);
/* Set the interrupt priority */
up_prioritize_irq(SH1_SYSTIMER_IRQ, 7); /* Set ITU priority midway */
/* Start the timer */
reg8 = getreg8(SH1_ITU_TSTR);
reg8 |= SH1_ITUTSTR_STR0; /* Enable TCNT0 */
putreg8(reg8, SH1_ITU_TSTR); /* TCNT0 is counting */
}
static int pic32mx_cninterrupt(int irq, FAR void *context)
{
int status;
int ret = OK;
int i;
/* Call all attached handlers */
for (i = 0; i < IOPORT_NUMCN; i++)
{
/* Is this one attached */
if (g_cnisrs[i])
{
/* Call the attached handler */
status = g_cnisrs[i](irq, context);
/* Keep track of the status of the last handler that failed */
if (status < 0)
{
ret = status;
}
}
/* Clear the pending interrupt */
up_clrpend_irq(PIC32MX_IRQ_CN);
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: pic32mx_gpioirqinitialize
*
* Description:
* Initialize logic to support a GPIO change notification interrupts.
* This function is called internally by the system on power up and should
* not be called again.
*
****************************************************************************/
void pic32mx_gpioirqinitialize(void)
{
int ret;
/* Attach the change notice interrupt handler */
ret = irqattach(PIC32MX_IRQ_CN, pic32mx_cninterrupt);
DEBUGASSERT(ret == OK);
/* Set the interrupt priority */
#ifdef CONFIG_ARCH_IRQPRIO
ret = up_prioritize_irq(PIC32MX_IRQ_CN, CONFIG_PIC32MX_CNPRIO);
DEBUGASSERT(ret == OK);
#endif
/* Reset all registers and enable the CN module */
putreg32(IOPORT_CN_ALL, PIC32MX_IOPORT_CNENCLR);
putreg32(IOPORT_CN_ALL, PIC32MX_IOPORT_CNPUECLR);
putreg32(IOPORT_CNCON_ON, PIC32MX_IOPORT_CNCON);
/* And enable the GPIO interrupt */
ret = up_enable_irq(PIC32MX_IRQSRC_CN);
DEBUGASSERT(ret == OK);
}
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
int (*handler)(int irq, void *context),
int source)
{
int vectorno;
DEBUGASSERT(dev != NULL);
DEBUGASSERT(source == 0);
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32F7_TIM1
case STM32_TIM1_BASE:
vectorno = STM32_IRQ_TIM1UP;
break;
#endif
#ifdef CONFIG_STM32F7_TIM2
case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
break;
#endif
#ifdef CONFIG_STM32F7_TIM3
case STM32_TIM3_BASE:
vectorno = STM32_IRQ_TIM3;
break;
#endif
#ifdef CONFIG_STM32F7_TIM4
case STM32_TIM4_BASE:
vectorno = STM32_IRQ_TIM4;
break;
#endif
#ifdef CONFIG_STM32F7_TIM5
case STM32_TIM5_BASE:
vectorno = STM32_IRQ_TIM5;
break;
#endif
#ifdef CONFIG_STM32F7_TIM6
case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif
#ifdef CONFIG_STM32F7_TIM7
case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
#endif
#ifdef CONFIG_STM32F7_TIM8
case STM32_TIM8_BASE:
vectorno = STM32_IRQ_TIM8UP;
break;
#endif
#ifdef CONFIG_STM32F7_TIM9
case STM32_TIM9_BASE:
vectorno = STM32_IRQ_TIM9;
break;
#endif
#ifdef CONFIG_STM32F7_TIM10
case STM32_TIM10_BASE:
vectorno = STM32_IRQ_TIM10;
break;
#endif
#ifdef CONFIG_STM32F7_TIM11
case STM32_TIM11_BASE:
vectorno = STM32_IRQ_TIM11;
break;
#endif
#ifdef CONFIG_STM32F7_TIM12
case STM32_TIM12_BASE:
vectorno = STM32_IRQ_TIM12;
break;
#endif
#ifdef CONFIG_STM32F7_TIM13
case STM32_TIM13_BASE:
vectorno = STM32_IRQ_TIM13;
break;
#endif
#ifdef CONFIG_STM32F7_TIM14
case STM32_TIM14_BASE:
vectorno = STM32_IRQ_TIM14;
break;
#endif
default:
return -EINVAL;
}
/* Disable interrupt when callback is removed */
if (!handler)
{
up_disable_irq(vectorno);
irq_detach(vectorno);
return OK;
}
/* Otherwise set callback and enable interrupt */
irq_attach(vectorno, handler);
up_enable_irq(vectorno);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
#endif
return OK;
}
