static void dma_si_read(struct si_controller* si)
{
int i;
if (si->regs[SI_PIF_ADDR_RD64B_REG] != 0x1FC007C0)
{
DebugMessage(M64MSG_ERROR, "dma_si_read(): unknown SI use");
return;
}
update_pif_read(si);
for (i = 0; i < PIF_RAM_SIZE; i += 4)
{
si->ri->rdram.dram[(si->regs[SI_DRAM_ADDR_REG]+i)/4] = sl(*(uint32_t*)(&si->pif.ram[i]));
}
cp0_update_count();
if (g_delay_si) {
add_interupt_event(SI_INT, /*0x100*/0x900);
} else {
si->regs[SI_STATUS_REG] |= 0x1000; // INTERRUPT
signal_rcp_interrupt(si->r4300, MI_INTR_SI);
}
}
void dma_si_read()
{
int i;
if (si_register.si_pif_addr_rd64b != 0x1FC007C0)
{
// printf("unknown SI use\n");
stop=1;
}
update_pif_read();
for (i=0; i<(64/4); i++)
rdram[si_register.si_dram_addr/4+i] = sl(PIF_RAM[i]);
update_count();
add_interupt_event(SI_INT, /*0x100*/0x900);
}
static void dma_si_read(struct si_controller* si)
{
int i;
if (si->regs[SI_PIF_ADDR_RD64B_REG] != 0x1FC007C0)
{
DebugMessage(si->r4300->state, M64MSG_ERROR, "dma_si_read(): unknown SI use");
si->r4300->state->stop=1;
}
update_pif_read(si);
for (i = 0; i < PIF_RAM_SIZE; i += 4)
{
si->ri->rdram.dram[(si->regs[SI_DRAM_ADDR_REG]+i)/4] = sl(*(uint32_t*)(&si->pif.ram[i]));
}
if (si->r4300->state->enable_trimming_mode)
{
for (i = 0; i < PIF_RAM_SIZE; i += 4)
{
unsigned int ram_address = si->regs[SI_DRAM_ADDR_REG] + i;
if (!bit_array_test(si->r4300->state->barray_ram_read, ram_address / 4))
bit_array_set(si->r4300->state->barray_ram_written_first, ram_address / 4);
}
}
update_count(si->r4300->state);
if (si->r4300->state->g_delay_si) {
add_interupt_event(si->r4300->state, SI_INT, /*0x100*/0x900);
} else {
si->regs[SI_STATUS_REG] |= 0x1000; // INTERRUPT
signal_rcp_interrupt(si->r4300, MI_INTR_SI);
}
}